LC75852W Schematic - Sanyo Semicon Device

LC75852W Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer	LC75852W
Beschreibung	Asynchronous Silicon Gate 1/2 Duty LCD Driver with On-Chip Key Input Function
Hersteller	Sanyo Semicon Device
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Gesamt 16 Seiten Ordering number : EN4828A CMOS LSI LC75852E, 75852W Asynchronous Silicon Gate 1/2 Duty LCD Driver with On-Chip Key Input Function Overview The LC75852E and LC75852W are 1/2 duty dynamic LCD display drivers. In addition to being able to directly drive LCD panels with up to 90 segments, they can also control up to four general-purpose output ports. These products also include a key scan circuit which allows them to accept input from keypads with up to 30 keys. This allows end product front panel wiring to be simplified. Features • Up to 30 key inputs (Key scan is only performed when a key is pressed.) • 1/2 duty – 1/2 bias (up to 90 segments) • Sleep mode and the all segments off function can be controlled from serial data. • Segment output port/general-purpose output port usage can be controlled from serial data. • Serial data I/O supports CCB format communication with the system controller. • High generality since display data is displayed directly without decoder intervention • Reset pin that can establish the initial state. Package Dimensions unit: mm 3159-QFP64E [LC75852E] unit: mm 3190-SQFP64 [LC75852W] SANYO: QIP64E • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V SANYO: SQFP64 Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT IOUT1 IOUT2 IOUT3 Pd max Topr Tstg Conditions VDD OSC, CE, CL, DI, RES, KI1 to KI5 OSC, DO, S1 to S45, COM1, COM2, KS1 to KS6, P1 to P4 S1 to S45 COM1, COM2, KS1 to KS6 P1 to P4 Ta = 85°C Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 100 1 5 200 –40 to +85 –55 to +125 Unit V V V µA mA mA mW °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63096HA (OT)/N1594TH (OT) B8-1326, 1328 No. 4828-1/16 LC75852E, 75852W Control Data Functions 1. S0, S1 .................Sleep control data This control data switches the LSI between normal mode and sleep mode. It also sets the key scan output standby states for pins KS1 to KS6. Control data S0 S1 Mode Oscillator Segment outputs Common outputs 0 0 Normal Oscillator Operation 0 1 Sleep Stopped L 1 0 Sleep Stopped L 1 1 Sleep Stopped L Note: The KS1/S44 and KS2/S45 output pins are set to the key scan output state. Key scan standby mode output pin states KS1 KS2 KS3 KS4 KS5 KS6 H HH H HH L LL L LH L L L L HH H HH H HH 2. K0, K1................Key scan output/segment output selection data This control data switches the KS1/S44 and KS2/S45 output pins between the key scan output and segment output functions. Control data K0 K1 00 01 1X X: don’t care Output pin states KS1/S44 KS2/S45 KS1 KS2 S44 KS2 S44 S45 Maximum number of key inputs 30 25 20 3. P0, P1 .................Segment output port/general-purpose output port selection data This control data switches the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port functions. Control data P0 P1 00 01 10 11 S1/P1 S1 P1 P1 P1 Output pin states S2/P2 S3/P3 S2 S3 P2 S3 P2 P3 P2 P3 S4/P4 S4 S4 S4 P4 The table below lists the correspondence between the display data and the output pins when the general-purpose output port function is selected. Output pin S1/P1 S2/P2 S3/P3 S4/P4 Corresponding display data D1 D3 D5 D7 For example, if the output pin S4/P4 is set for use as a general-purpose output port, the output pin S4/P4 will output a high level when the display data D7 is 1. 4. SC.......................Segment on/off control data This control data controls the segment on/off states. SC Display state 0 On 1 Off No. 4828-6/16 6 Page LC75852E, 75852W Internal Block States during the Reset Period (when RES is low) 1. CLOCK GENERATOR Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is determined after the control data S0 and S1 has been sent. 2. COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the LATCH. 3. KEY SCAN Reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is disabled. 4. KEY BUFFER Reset is applied and all the key data is set to the low level. 5. CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER To allow serial data transfers, reset is not applied to these circuits. Output Pin States during the Reset Period (when RES is low) Output pin State during reset S1/P1 to S4/P4 L3 S5 to S43 L COM1, COM2 L KS1/S44, KS2/S45 L3 KS3 to KS5 X4 KS6 H DO H5 X: don’t care Note: 3. These output pins are forcibly set to the segment output mode and held low. 4. Immediately following power on, these output pins are undefined until the control data S0 and S1 has been sent. 5. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin is held high during the reset period even if key data is read. No. 4828-12/16 12 Page
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Besondere Datenblatt

Teilenummer	Beschreibung	Hersteller
LC75852E	Asynchronous Silicon Gate 1/2 Duty LCD Driver with On-Chip Key Input Function	Sanyo Semicon Device
LC75852E	Asynchronous Silicon Gate 1/2 Duty LCD Driver	ON Semiconductor
LC75852W	Asynchronous Silicon Gate 1/2 Duty LCD Driver with On-Chip Key Input Function	Sanyo Semicon Device
LC75852W	Asynchronous Silicon Gate 1/2 Duty LCD Driver	ON Semiconductor

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