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S71PL129JC0 Schematic ( PDF Datasheet ) - SPANSION

Teilenummer S71PL129JC0
Beschreibung Stacked Multi-Chip Product (MCP) Flash Memory
Hersteller SPANSION
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Gesamt 30 Seiten
S71PL129JC0 Datasheet, Funktion
www.DataSheet4U.com
S71PL129JC0/S71PL129JB0/S71PL129JA0
Stacked Multi-Chip Product (MCP) Flash Memory and
pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation, Page Mode Flash Memory with
64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM
Data Sheet
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71PL129Jxx_00 Revision A Amendment 8 Issue Date October 28, 2005






S71PL129JC0 Datasheet, Funktion
Advance Information
RY/BY#: Ready/Busy# .......................................................................................58
DQ6: Toggle Bit I ............................................................................................... 58
Figure 7. Toggle Bit Algorithm.............................................. 60
DQ2: Toggle Bit II .............................................................................................. 60
Reading Toggle Bits DQ6/DQ2 ..................................................................... 60
DQ5: Exceeded Timing Limits ........................................................................ 61
DQ3: Sector Erase Timer ................................................................................. 61
Table 14. Write Operation Status ......................................... 62
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 63
Figure 8. Maximum Overshoot Waveforms............................. 63
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .64
Industrial (I) Devices ......................................................................................... 64
Extended (E) Devices ........................................................................................ 64
Supply Voltages ................................................................................................... 64
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 15. CMOS Compatible ................................................ 65
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .66
Test Conditions .................................................................................................. 66
Figure 9. Test Setups......................................................... 66
Table 16. Test Specifications ............................................... 66
Switching Waveforms ....................................................................................... 66
Table 17. Key to Switching Waveforms ................................. 66
Figure 10. Input Waveforms and Measurement Levels............. 67
VCC RampRate ...................................................................................................67
Read Operations .................................................................................................67
Table 18. Read-Only Operations .......................................... 67
Figure 11. Read Operation Timings ....................................... 68
Figure 12. Page Read Operation Timings ............................... 68
Reset ...................................................................................................................... 69
Table 19. Hardware Reset (RESET#) .................................... 69
Figure 13. Reset Timings..................................................... 69
Erase/Program Operations ............................................................................. 70
Table 20. Erase and Program Operations .............................. 70
Timing Diagrams ...................................................................................................71
Figure 14. Program Operation Timings .................................. 71
Figure 15. Accelerated Program Timing Diagram .................... 71
Figure 16. Chip/Sector Erase Operation Timings ..................... 72
Figure 17. Back-to-back Read/Write Cycle Timings ................. 73
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 73
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 74
Figure 20. DQ2 vs. DQ6 ...................................................... 74
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 21. Temporary Sector Unprotect ................................. 75
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 75
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 76
Controlled Erase Operations ..........................................................................77
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 77
Table 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 78
Table 24. CE1#/CE2# Timing ............................................. 78
Figure 23. Timing Diagram for Alternating Between CE1# and CE2#
Control ............................................................................. 79
Table 25. Erase And Programming Performance .................... 79
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 79
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Functional Description . . . . . . . . . . . . . . . . . . . . . 81
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . 81
AC Characteristics and Operating Conditions . 82
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 83
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Read Timings ........................................................................................................84
Figure 24. Read Cycle ........................................................ 84
Figure 25. Page Read Cycle (8 Words Access) ....................... 85
Write Timings ......................................................................................................86
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 86
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 87
Deep Power-down Timing ..............................................................................87
Figure 28. Deep Power Down Timing .................................... 87
Power-on Timing ................................................................................................87
Figure 29. Power-on Timing ................................................ 87
Provisions of Address Skew ............................................................................88
Read ....................................................................................................................88
Figure 30. Read................................................................. 88
Write ..................................................................................................................88
Figure 31. Write ................................................................ 88
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 89
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 95
Output Load Circuit ..........................................................................................96
Figure 32. Output Load Circuit............................................. 96
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 96
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 108
Read Cycle .......................................................................................................... 108
Figure 33. Timing of Read Cycle
(CE# = OE# = VIL, WE# = ZZ# = VIH) .............................. 108
Figure 34. Timing Waveform of Read Cycle
(WE# = ZZ# = VIH)......................................................... 109
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = VIH)......................................................... 110
Write Cycle ...........................................................................................................111
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = VIH)................................................ 111
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = VIH)................................................. 111
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = VIH) ................................................................... 112
Partial Array Self Refresh (PAR) ....................................................................112
Temperature Compensated Refresh (for 64Mb) .....................................113
Deep Sleep Mode ...............................................................................................113
Reduced Memory Size (for 32M and 16M) ..................................................113
Other Mode Register Settings (for 64M) ....................................................113
Figure 39. Mode Register .................................................. 114
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 114
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 115
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 115
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Product Information . . . . . . . . . . . . . . . . . . . . . . 119
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 120
4
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005

6 Page









S71PL129JC0 pdf, datenblatt
Advance Information
www.DataSheet4U.com
Base Ordering
Part Number
S71PL129JA0
S71PL129JB0
S71PL129JB0
S71PL129JB0
S71PL129JC0
S71PL129JC0
S71PL129JC0
S71PL129JA0
S71PL129JB0
S71PL129JB0
S71PL129JB0
S71PL129JC0
S71PL129JC0
S71PL129JC0
S71PL129J Valid Combinations
Package &
Temperature
Package Modifier/
Model Number
9P
9Z
9B
BAW
9U
9B
9Z
9U
9P
9Z
9B
BFW
9U
9B
9Z
9U
Packing Type
0, 2, 3 (Note 1)
0, 2, 3 (Note 1)
Speed Options
(ns)
65
65
(p)SRAM
Type/Access
Time (ns)
pSRAM 7 / 70
pSRAM 7 / 70
pSRAM 2 / 70
pSRAM 6 / 70
pSRAM 2 / 70
pSRAM 7 / 70
pSRAM 6 / 70
pSRAM 7 / 70
pSRAM 7 / 70
pSRAM 2 / 70
pSRAM 6 / 70
pSRAM 2 / 70
pSRAM 7 / 70
pSRAM 6 / 70
Package
Marking
(Note 2)
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
3. Contact factory for availability of any of the above OPNs. RAM
type availability may vary over time.
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
10
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005

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