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79RC32435 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 79RC32435
Beschreibung IDTTM InterpriseTM Integrated Communications Processor
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
79RC32435 Datasheet, Funktion
IDTTM InterpriseTM Integrated
Communications Processor
www.DataSheet4U.com
79RC32435
Device Overview
The 79RC32435 is a member of the IDT™ Interprise™ family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention, using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32435 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
Features
x 32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 8KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
– 3-entry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop, and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– ICE Interface that is compatible with v2.5 of the EJTAG Spec-
ification
x PCI Interface
– 32-bit PCI revision 2.2 compliant
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
– I2O “like” PCI Messaging Unit
x Ethernet Interface
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Supports MII or RMII PHY interface
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
1997
x DDR Memory Controller
– Supports up to 256MB of DDR SDRAM
– 1 chip select supporting 4 internal DDR banks
– Supports a 16-bit wide data port using x8 or x16 bit wide DDR
SDRAM devices
– Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
Block Diagram
ICE
DDR
(16-bit)
MIPS-32
CPU Core
EJTAG
D. Cache
MMU
I. Cache
PMBus
DDR
Controllers
MII/RMII
Interrupt
Controller
:
:
3 Counter
Timers
1 Ethernet
10/100
Interface
IPBusTM
I2C Bus
I2C
Controller
NVRAM
Controller
DMA
Controller
Arbiter
Memory & I/O
Controller
Bus/System
Integrity
Monitor
1 UART
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus (8-bit)
Serial Channel GPIO Pins SPI Bus
PCI Bus
2005 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 53
January 19, 2006
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79RC32435 Datasheet, Funktion
IDT 79RC32435
Signal
Type
Name/Description
www.DataSheet4U.com
PCILOCKN
I/O PCI Lock. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCIPAR
I/O PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCIPERRN
I/O PCI Parity Error. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
PCIREQN[3:0]
I/O PCI Bus Request.
In PCI host mode with internal arbiter:
These signals are inputs whose assertion indicates to the internal RC32435
arbiter that an agent desires ownership of the PCI bus.
In PCI host mode with external arbiter:
PCIREQN[0]: asserted by the RC32435 to request ownership of the PCI bus.
PCIREQN[3:1]: unused and driven high.
In PCI satellite mode:
PCIREQN[0]: this signal is asserted by the RC32435 to request use of the PCI
bus.
PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during
configuration read and write transactions.
PCIREQN[3:2]: unused and driven high.
PCIRSTN
I/O PCI Reset. In host mode, this signal is asserted by the RC32435 to generate a
PCI reset. In satellite mode, assertion of this signal initiates a warm reset.
PCISERRN
I/O PCI System Error. This signal is driven by an agent to indicate an address par-
ity error, data parity error during a special cycle command, or any other system
error. Requires an external pull-up.
PCISTOPN
I/O PCI Stop. Driven by the bus target to terminate the current bus transaction. For
example, to indicate a retry.
PCITRDYN
I/O PCI Target Ready. Driven by the bus target to indicate that the current data can
complete.
General Purpose Input/Output
GPIO[0]
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SOUT
Alternate function: UART channel 0 serial output.
GPIO[1]
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SINP
Alternate function: UART channel 0 serial input.
GPIO[2]
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0RTSN
Alternate function: UART channel 0 request to send.
GPIO[3]
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0CTSN
Alternate function: UART channel 0 clear to send.
Table 1 Pin Description (Part 3 of 6)
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79RC32435 pdf, datenblatt
IDT 79RC32435
Boot Configuration Vector
www.DataSheet4U.com
The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configura-
tion vector read in by the RC32435 during a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register.
Signal
MADDR[3:0]
MADDR[5:4]
MADDR[6]
MADDR[7]
MADDR[10:8]
Name/Description
CPU Pipeline Clock Multiplier. This field specifies the value by which the PLL multi-
plies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For
master clock input frequency constraints, refer to Table 3.2 in the RC32435 User Man-
ual.
0x0 - PLL Bypass
0x1 - Multiply by 3
0x2 - Multiply by 4
0x3 - Multiply by 5 - Reserved
0x4 - Multiply by 5
0x5 - Multiply by 6 - Reserved
0x6 - Multiply by 6
0x7 - Multiply by 8
0x8 - Multiply by 10
0x9 through 0xF - Reserved
External Clock Divider. This field specifies the value by which the IPBus clock
(ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock
output on the EXTCLK pin.
0x0 - Divide by 1
0x1 - Divide by 2
0x2 - Divide by 4
0x3 - reserved
Endian. This bit specifies the endianness.
0x0 - little endian
0x1 - big endian
Reset Mode. This bit specifies the length of time the RSTN signal is driven.
0x0 - Normal reset: RSTN driven for minimum of 4000 clock cycles. If the internal boot
configuration vector is selected, the expiration of an 18-bit counter operating at the
master clock input (CLK) frequency is used as the PLL stabilization delay.
0x1 - Reserved
PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial
value of the EN bit in the PCIC register is determined by the PCI mode.
0x0 - Disabled (EN initial value is zero)
0x1 - PCI satellite mode with PCI target not ready (EN initial value is one)
0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one)
0x3 - PCI host mode with external arbiter (EN initial value is zero)
0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm
(EN initial value is zero)
0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm
(EN initial value is zero)
0x6 - reserved
0x7 - reserved
Table 3 Boot Configuration Encoding (Part 1 of 2)
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