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ADV7330 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7330
Beschreibung Multiformat 11-Bit Triple DAC Video Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7330 Datasheet, Funktion
FEATURES
High Definition Input Formats
8-Bit or 16-Bit (4:2:2) Parallel YCrCb Compliant with:
SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (525p/625p)
ITU-R BT.1362 (525p/625p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
Other High Definition Formats Using Async
Timing Mode
High Definition Output Formats
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision® Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-Bit or 16-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference
Three 11-Bit Precision Video DACs
2-Wire Serial I2C® Interface, Open Drain Configuration
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product
Multiformat 11-Bitwww.DataSheet4U.com
Triple DAC Video Encoder
ADV7330
APPLICATIONS
SD/PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
Y7–Y0
C7–C0
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
CLKIN
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
D
E
M
U
X
TIMING
GENERATOR
PROGRAMMABLE
RGB MATRIX
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7330
O 11-BIT
V DAC
E
R
S
A 11-BIT
M DAC
P
L
I
N
G
11-BIT
DAC
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV®7330 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes three high speed video D/A
converters with TTL compatible inputs.
The ADV7330 has separate 8-bit or 16-bit input ports that
accept data in high definition or standard definition video
format. For all standards, external horizontal, vertical, and
blanking signals or EAV/SAV timing codes control the inser-
tion of appropriate synchronization signals into the digital
data stream and therefore the output signal.
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.






ADV7330 Datasheet, Funktion
ADV7330
www.DataSheet4U.com
TIMING SPECIFICATIONS (VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V,
RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0؇C to 70؇C), unless otherwise noted.)
Parameter
Min Typ Max Unit
Conditions
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
0
0.6
1.3
0.6
0.6
100
0.6
100
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
After this period, the first clock is generated
Relevant for repeated start condition
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
7 ns
1 ns
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t111
Data Hold Time, t121
SD Output Access Time, t13
SD Output Hold Time, t14
HD Output Access Time, t13
HD Output Hold Time, t14
PIPELINE DELAY4
40
40
2.0
2.0
5.0
5.0
27
81
15
14
63
76
35
41
36
MHz
Progressive scan mode
MHz
HDTV mode/async mode
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD (2×, 16×)
SD component mode (16×)
PS (1×)
PS (8×)
HD (2×, 1×)
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of the DAC output full-scale transition.
3Data: C [9:0]; Y [9:0], S[9:0].
Control: HSYNC_I/P, VSYNC_I/P, BLANK_I/P, HSYNC_O/P, VSYNC_O/P, BLANK_O/P.
4SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.
–6– REV. B

6 Page









ADV7330 pdf, datenblatt
ADV7330
PIN CONFIGURATION
www.DataSheet4U.com
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_IO 1
TEST0 2
TEST1 3
Y0 4
Y1 5
Y2 6
Y3 7
Y4 8
Y5 9
VDD 10
DGND 11
Y6 12
Y7 13
TEST2 14
TEST3 15
C0 16
PIN 1
IDENTIFIER
ADV7330
TOP VIEW
(Not to Scale)
48 BLANK_O/P
47 TEST16
46 VREF
45 TEST15
44 NC
43 NC
42 NC
41 VAA
40 AGND
39 DAC A
38 DAC B
37 DAC C
36 COMP
35 RSET
34 EXT_LF
33 RESET
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Pin Number
11, 57
2, 3, 14, 15,
51–55, 58–63
40
32
36
39
38
37
25
23
24
4–9, 12, 13
16–18, 26–30
33
35
22
21
20
1
PIN FUNCTION DESCRIPTIONS
Mnemonic
I/O Function
DGND
G Digital Ground.
TEST0–TEST14 I
Not used, tie to DGND.
AGND
CLKIN
COMP
DAC A
DAC B
DAC C
BLANK_I/P
HSYNC_I/P
VSYNC_I/P
Y7–Y0
C7–C0
RESET
RSET
SCLK
SDA
ALSB
VDD_IO
G Analog Ground.
I Pixel Clock Input for HD (74.25 MHz Only, PS (27 MHz), SD (27 MHz)).
O Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to VAA.
O CVBS/GREEN/Y Analog Output.
O Chroma/BLUE/Pb Analog Output.
O Luma/RED/Pr Analog Output.
I Video Blanking Control Signal. For HD and PS, this input is active high. For SD
input, this input is active low.
I Video Horizontal Sync Control Signal.
I Video Vertical Sync Control Signal.
I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved
progressive scan data. The LSB is set up on Pin Y0.
I 8-Bit SD/Progressive Scan/HDTV Input Port. The LSB is set up on Pin C0.
I This input resets the on-chip timing generator and sets the ADV7330 into the default
register setting. Reset is an active low signal.
I A 3040 resistor must be connected from this pin to AGND and is used to control
the amplitudes of the DAC outputs.
I I2C Port Serial Interface Clock Input.
I/O I2C Port Serial Data Input/Output.
I TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is
tied low, the I2C filter is activated, which reduces noise on the I2C interface.
P Power Supply for Digital Inputs and Outputs.
–12–
REV. B

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