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LX128V Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer LX128V
Beschreibung High Performance Interfacing and Switching
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 30 Seiten
LX128V Datasheet, Funktion
www.DataSheet4U.com
ispGDX2Family
Includes
High-
High Performance Interfacing and Switching
September 2005
Features
Performance,
Low-Cost
“E-Series” Two Options Available
Data Sheet
• High-performance sysHSI (standard part number)
High Performance Bus Switching
• Low-cost, no sysHSI (“E-Series”)
• High bandwidth
– Up to 12.8 Gbps (SERDES)
sysHSI Blocks Provide up to 16 High-speed
– Up to 38 Gbps (without SERDES)
Channels
• Up to 16 (15x10) FIFOs for data buffering
• Serializer/de-serializer (SERDES) included
• High speed performance
• Clock Data Recovery (CDR) built in
– fMAX = 360MHz
– tPD = 3.0ns
– tCO = 2.9ns
– tS = 2.0ns
• Built-in programmable control logic capability
• 800 Mbps per channel
• LVDS differential support
• 10B/12B support
– Encoding / decoding
– Bit alignment
• I/O intensive: 64 to 256 I/Os
– Symbol alignment
• Expanded MUX capability up to 188:1 MUX
• 8B/10B support
– Bit alignment
sysCLOCK™ PLL
– Symbol alignment
• Frequency synthesis and skew management
• Source Synchronous support
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps steps
Flexible Programming and Testing
• Up to four PLLs
• IEEE 1532 compliant In-System Programmabil-
ity (ISP™)
sysIO™ Interfacing
• Boundary scan test through IEEE 1149.1
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
interface
standard board interfaces
• 3.3V, 2.5V or 1.8V power supplies
• SSTL 2/3 Class I and II support
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
• HSTL Class I, III and IV support
interfaces
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os 64 128 256
GDX Blocks
4 8 16
tPD
tS
tCO
fMAX (Toggle)
Max Bandwidth
sysHSI Channels2
SERDES1, 2
Without SERDES3
3.0ns
2.0ns
2.9ns
360MHz
3.2Gbps
11Gbps
4
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
LVDS/Bus LVDS (Pairs)
32 64 128
PLLs
224
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13






LX128V Datasheet, Funktion
Lattice Semiconductor
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A
fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX
sizes and delay levels.
Table 2. MUX Size Versus Internal Delay
MUX Sizes
4:1
Up to 16:1
Up to 64:1
Up to 188:1 (with ispGDX2-256)
Levels of Internal GRP Delays
One Level
Two Levels
Three Levels
Four Levels
Figure 3. ispGDX2 Family MRB
MUX Select
Control Array Signals
Global
Signals
4 2-4
GDX
Control Array
24 2
OE
MUX
Select
Global
Signals
CK
CE
D/L Q
ClK OE
Reg/Latch
CE
Set
VCC
Reset
TOE
Flags*
(FIFO, SERDES
or PLL)
From GRP
from
Out_Reg(n-1)
from
Out_Reg(n+1)
D/L Q
ClK Out
Reg/Latch
CE
Set Reset
VCC
S/R
Global Resetb
to Out_Reg(n-1)
to Out_Reg(n+1)
To GRP
Delay
FIFO Out*
from IN_Reg(n-1)
from IN_Reg(n+1)
CK
CE
S/R
*Selected MRBs see Logic Signal Connection Table for details
D/L Q
ClK Input
Reg/Latch
CE
Set
Reset
Global Resetb
to IN_Reg(n-1)
to IN_Reg(n+1)
Control Array
The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms
of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs
to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE sig-
nals. Figure 4 illustrates the control array.
6

6 Page









LX128V pdf, datenblatt
Lattice Semiconductor
Figure 8. ispGDX2-64 CLOCK Network
sysIO Interface
GCLK/CE0
VREF0
CLK_OUT0
GCLK/CE1
VREF1
CLK_OUT2
GCLK/CE2
VREF2
+
-
+
-
+
-
sysCLOCK
CLK0
K(0)
PLL
(0)
CLK2
K(2)
PLL
(2)
GCLK/CE3
VREF3
+
-
Figure 9. ispGDX2-128 CLOCK Network
sysIO Interface
GCLK/CE0
VREF0
CLK_OUT0
GCLK/CE1
VREF1
CLK_OUT2
GCLK/CE2
VREF2
GCLK/CE3
VREF3
+
-
+
-
+
-
+
-
sysCLOCK
CLK0
K(0)
PLL
(0)
CLK2
K(2)
PLL
(2)
12
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
Clock Net
MRB
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
MRB
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch

12 Page





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