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WC32P040-XXM Schematic ( PDF Datasheet ) - White Electronic Designs Corporation

Teilenummer WC32P040-XXM
Beschreibung 32-Bit Nonmultiplexed External Address and Data Buses
Hersteller White Electronic Designs Corporation
Logo White Electronic Designs Corporation Logo 




Gesamt 23 Seiten
WC32P040-XXM Datasheet, Funktion
White Electronic Designs
WC32P040-XXM
www.DataSheet4U.com
68040 FEATURES
Selection of Processor Speeds: 25, 33MHz
Military Temperature Range: -55°C to +125°C
Packaging
• 179 pin Ceramic PGA (P4)
• 184 lead Ceramic Quad Flatpack, CQFP (Q4)
6-Stage Pipeline, 68030-Compatible IU
68881/68882-Compatible FPU
Independent Instruction and Data MMUs
Simultaneously Accessible, 4-Kbyte Physical
Instruction Cache and 4-Kbyte Physical Data Cache
Low-Latency Bus Acceses for Reduced Cache Miss
Penalty
Multimaster/Multiprocessor Support via Bus
Snooping
Concurrent IU, FPU, MMU, and Bus Controller
Operation Maximizes Throughput
32-Bit, Nonmultiplexed External Address and Data
Buses with Synchronous Interface
User Object-Code Compatible with all Earlier 68000
Microprocessors
4-GigaByte Direct Addressing Range
DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance,
32-bit microprocessor. The WC32P040 is a virtual
memory microprocessor employing multiple concurrent
execution units and a highly intergrated architecture that
provides very high performance in a monolithic HCMOS
device. It has a 68030-compatible integer unit (IU) and
two independent caches. The WC32P040 contains dual,
independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and
independent, 4-Kbyte instruction and data caches. The
WC32P040 has a 68881/68882-compatible floating-point
unit (FPU).
FIGURE 1 – BLOCK DIAGRAM
INSTRUCTION DATA BUS
CONVERT
EXECUTE
WRITE-
BACK
FLOATING-
POINT
UNIT
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EA
FETCH
EXECUTE
WRITE-
BACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
INSTRUCTION
ADDRESS
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
DATA
ADDRESS
B
U
S
C
O
N
T
R
O
L
L
E
R
DATA
ATC
DATA
CACHE
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
JJuulyly19199898
OPERAND DATA BUS
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WC32P040-XXM Datasheet, Funktion
White Electronic Designs
WC32P040-XXM
www.DataSheet4U.com
Opcode
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT,EXTB
FABS
FADD
FBcc
FCMP
FDBcc
FDIV
FMOVE
INSTRUCTION SET SUMMARY (contd)
Operation
If condition false
then (Dn-1 Dn;
if (Dn ≠ -1
then PC + dn PC)
Destination + Source Destination
Destination + Source Destination
Source Destination Destination
Immediate Data Destination Destination
Source CCR CCR
If supervisor state
Rx Ry
Destination Sign – Extended Destination
Absolute Value of Source FPn
Source + FPn FPn
If condition true
then PC + dn PC
FPn – Source
It condition true
then no operation
else Dn-1 Dn
if Dn ≠ -1
then PC + dn PC
else execute next instruction
FPn + Source FPn
Source Destination
Syntax
DBcc Dn,<label>
DIVS.W <ea>,Dn
DIVS.L <ea>,Dq
DIVS.L <ea>,Dr:Dq
DIVSL.L <ea>,Dr:Dq
32 + 16
32 + 32
64 + 32
32 + 32
16r:16q
32q
32r:32q
32r:32q
DIVU.W <ea>,Dn
DIVU.L <ea>,Dq
DIVU.L <ea>,Dr:Dq
DIVUL.L <ea>,Dr:Dq
32 + 16
32 + 32
64 + 32
32 + 32
16r:16q
32q
32r:32q
32r:32q
EOR Dn,<ea>
EORI #<data>,<ea>
EORI #<data>,CCR
EORI #<data>,SR
then Source SR SR
else TRAP
EXG Dx,Dy
EXG Ax,Ay
EXG Dx,Ay
EXG Ay,Dx
EXT.W Dn
EXT.L L Dn
EXTB.L Dn
extend byte to word
extend word to long word
extend byte to long word
FABS.<fmt> <ea>,FPn
FABS.X FPm,FPn
FABS.X FPn
FrABS.<fmt> <ea>,FPn(2)
FrABS.X FPm,FPn(2)
FrABS.X FPn(3)
FADD.<fmt, <ea>,FPn
FADD.X FPm,FPn
FrADD.<fmt> <ea>,FPn(2)
FrADD.X FPm,FPn(2)
FBcc.SIZE <label>
FCMP.<fmt> <ea>,FPn
FCMP.X FPm,FPn
FDBcc Dn,<label>
FDIV.<tmt> <ea>,FPn
FDIV.X FPm,FPn
FrDIV.<fmt> <ea>,FPn(2)
FrDIV.X FPm,FPn(2)
FMOVE.<fmt> <ea>,FPn
FMOVE.<fmt> FPM,<ea>
FMOVE.P FPm,<ea>{Dn}
FMOVE.P FPm,<ea>{#k}
FrMOVE.<fmt> <ea>,FPn(2)
July 1998
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WC32P040-XXM pdf, datenblatt
White Electronic Designs
WC32P040-XXM
www.DataSheet4U.com
SIGNAL INDEX
Signal Name
Address Bus
Data Bus
Transfer Type
Transfer Modifier
Transfer Line Number
User-Progammable Attributes
Read/Write
Transfer Size
Bus Lock
Bus Lock End
Cache Inhibit Out
Transfer Start
Transfer on Progress
Transfer Acknowledge
Transfer Error Acknowledge
Transfer Cache Inhibit
Transfer Burst Inhibit
Data Latch Enable
Snoop Control
Memory Inhibit
Bus Request
Bus Grant
Bus Busy
Cache Disable
MMU Disable
Reset In
Reset Out
Interrupt Priority Level
Interrupt Pending
Autovector
Processor Status
Processor Clock
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Test Reset
Power Supply
Ground
Mnemonic
A31-A0
D31-D0
TT1,TT0
TM2-TM0
TLN1-TLN0
UPA1,UPA0
R/W#
SIZ0/SIZ1
LOCK#
LOCKE#
CIOUT#
TS#
TIP#
TA#
TEA#
TCI#
TBI#
DLE
SC1,SC0
MI#
BR#
BG#
BB#
CDIS#
MDIS#
RSTI#
RSTO#
IPL2#-IPL0#
IPEND#
AVEC#
PST3-PST0
PCLK
TCK
TMS
TDI
TDO
TRST#
Vcc
GND
Function
32-bit address bus used to address any of 4-Gbytes.
32-bit data bus used to transfer up to 32 bits of data per bus transfer.
Indicates the general transfer type: normal, MOVE16, alternate logical function code, and acknowledge.
Indicates supplemental information about the access.
Indicates which cache line in a set is being pushed or loaded by the current line transfer.
User-defined signals, controlled by the corresponding user attribute bits from the address translation entry.
Identifies the transfer as a read or write.
Indicates the data transfer size. These signals, together with A0 and A1, define the active sections of the data
bus.
Indicates a bus transfer is part of a read-modify-write operation, and the sequence of transfers should be
interrupted.
Indicates the current transfer is the last in a locked sequence of transfers.
Indicates the processor will not cache the current bus transfer.
Indicates the beginning of the bus transfer.
Asserted for the duration of a bus transfer.
Asserted to acknowledge a bus transfer.
Indicates an error condition exists for a bus transfer.
Indicates the current bus transfer should not be cached.
Indicates the slave cannot handle a line burst access.
Alternate clock input used to latch input data when the processor is operating in DLE mode.
Indicates the snooping operation required during an alternate master access.
Inhibits mem ory devices from responding to an alternate master access during snooping operations.
Asserted by the processor to request bus mastership.
Asserted by an arbiter to grant bus mastership to the processor.
Asserted by the current bus master to indicate it has assumed ownership of the bus.
Dynamically disables the internal caches to assist emulator support.
Disables the translation mechanism of the MMUs.
Processor reset.
Asserted during execution of a RESET instruction to reset external devices.
Provides an encoded interrupt level to the processor.
Indicates an interrupt is pending.
Used during an interrupt acknowledge transfer to request internal generation of the vector number.
Indicates internal processor status.
Clock input used for internal logic timing. The PCLK frequency is exactly 2 x the BLCK frequency.
Clock signal for the IEEE P1149.1 Test Access Port (TAP).
Selects the principle operations of the test-support circuitry.
Serial data input for the TAP.
Serial data output for the TAP.
Provides an asynchronous reset of the TAP controller.
Power supply.
Ground connection.
July 1998
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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