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PDF ZL2106 Data sheet ( Hoja de datos )
| Número de pieza | ZL2106 | |
| Descripción | 6A Digital-DC Synchronous Step-Down DC-DC Converter | |
| Fabricantes | Intersil Corporation | |
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6A Digital-DC Synchronous Step-Down DC/DC Converter
ZL2106
The ZL2106 is a digital power conversion and management IC
that combines an integrated synchronous step-down DC/DC
converter with key power management functions in a small
package, resulting in a flexible and integrated solution.
The ZL2106 can provide an output voltage from 0.54V to 5.5V
(with margin) from an input voltage between 4.5V and 14V.
Internal low rDS(ON) synchronous power MOSFETs enable the
ZL2106 to deliver continuous loads up to 6A with high
efficiency. An internal Schottky bootstrap diode reduces
discrete component count. The ZL2106 also supports phase
spreading to reduce system input capacitance.
Power management features such as digital soft-start delay
and ramp, sequencing, tracking, and margining can be
configured by simple pin-strapping or through an on-chip serial
port. The ZL2106 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for interoperability between other Zilker Labs devices.
Features
• Integrated MOSFET switches
• 6A continuous output current
• ±1% output voltage accuracy
• Snapshot™ parametric capture
• I2C/SMBus interface, PMBus compatible
• Internal non-volatile memory (NVM)
Applications
• Telecom, Networking, Storage equipment
• Test and Measurement equipment
• Industrial control equipment
• 5V and 12V distributed power systems
Related Literature
• AN1468 “ZL2106EVAL1Z Evaluation Board”, USB Adapter
Board, GUI Software
• AN2010 “Thermal and Layout Guidelines for Digital-DC™
Products”
• AN2033 “Zilker Labs PMBus Command Set-DDC
ProductsPMBus Command Set”
• AN2035 “Compensation Using CompZL™”
100
VOUT = 3.3V
90
80
70
60
VIN = 12V
50 fSW = 200kHz
L = 6µH
40
0.0 1.0 2.0
3.0
IOUT (A)
4.0
FIGURE 1. ZL2106 EFFICIENCY
5.0
6.0
February 20, 2013
FN6852.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2009 -2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ZL2106
Pin Descriptions (Continued)
TYPE
PIN
LABEL
(Note 1)
DESCRIPTION
31 VR PWR Regulated bias from internal 7V low-dropout regulator (return is PGND). Decouple with a 4.7µF capacitor to
PGND.
32 VRA PWR Regulated bias from internal 5V low-dropout regulator for internal analog circuitry (return is SGND).
Decouple with a 4.7µF capacitor to SGND.
33
V2P5
PWR Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry (return is DGND).
Decouple with a 10µF capacitor.
34 DDC I/O Digital-DC Bus (open drain). Interoperability between Zilker Labs devices.
35 MGN
I Margin pin. Used to enable margining of the output voltage.
36 EN
I Enable pin. Used to enable the device (active high).
ePad
SGND
PWR Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane.
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pins. Please refer to Section “Multi-mode Pins” on page 11.
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
Ordering Information
PART NUMBER
(Note 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
PKG.
DWG. #
ZL2106ALCF (Note 2)
2106
-40 to +85
36 Ld 6mmx6mm QFN
L36.6x6C
ZL2106ALCFT (Notes 1, 2)
2106
-40 to +85
36 Ld 6mmx6mm QFN
L36.6x6C
ZL2106ALCFTK (Notes 1, 2)
2106
-40 to +85
36 Ld 6mmx6mm QFN
L36.6x6C
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ZL2106. For more information on MSL please see techbrief TB363.
5 FN6852.6
February 20, 2013
5 Page 
ZL2106
The ZL2106 integrates two N-channel power MOSFETs; QH is the
top control MOSFET and QL is the bottom synchronous MOSFET.
The amount of time that QH is on as a fraction of the total
switching period is known as the duty cycle D, which is described
by Equation 1:
D ≈ VOUT
VIN
(EQ. 1)
During time D, QH is on and VIN – VOUT is applied across the
inductor. The output current ramps up as shown in Figure 12.
When QH turns off (time 1-D), the current flowing in the inductor
must continue to flow from the ground up through QL, during which
the current ramps down. Since the output capacitor COUT exhibits
low impedance at the switching frequency, the AC component of the
inductor current is filtered from the output voltage so the load sees
nearly a DC voltage.
The maximum conversion ratio is shown in Figure 9. Typically,
buck converters specify a maximum duty cycle that effectively
limits the maximum output voltage that can be realized for a
given input voltage and switching frequency. This duty cycle limit
ensures that the low-side MOSFET is allowed to turn on for a
minimum amount of time during each switching cycle, which
enables the bootstrap capacitor to be charged up and provide
adequate gate drive voltage for the high-side MOSFET.
VIN - VOUT
ILPK
0 IO
-VOUT
ILV
D 1-D
Time
FIGURE 12. INDUCTOR WAVEFORM
In general, the size of components L1 and COUT as well as the
overall efficiency of the circuit are inversely proportional to the
switching frequency, fSW. Therefore, the highest efficiency circuit
may be realized by switching the MOSFETs at the lowest possible
frequency; however, this will result in the largest component size.
Conversely, the smallest possible footprint may be realized by
switching at the fastest possible frequency but this gives a
somewhat lower efficiency. Each user should determine the
optimal combination of size and efficiency when determining the
switching frequency for each application.
The block diagram for the ZL2106 is illustrated in
Figure 11. In this circuit, the target output voltage is regulated by
connecting the VSEN pin directly to the output regulation point.
The VSEN signal is then compared to an internal reference
voltage that had been set to the desired output voltage level by
the user. The error signal derived from this comparison is
converted to a digital value with an analog to digital (A/D)
converter. The digital signal is also applied to an adjustable
digital compensation filter and the compensated signal is used
to derive the appropriate PWM duty cycle for driving the internal
MOSFETs in a way that produces the desired output.
Power Management Overview
The ZL2106 incorporates a wide range of configurable power
management features that are simple to implement without
additional components. Also, the ZL2106 includes circuit protection
features that continuously safeguard the device and load from
damage due to unexpected system faults. The ZL2106 can
continuously monitor input voltage, output voltage/current and
internal temperature. A Power-good output signal is also included to
enable power-on reset functionality for an external processor.
All power management functions can be configured using either
pin configuration techniques (see Figure 13) or via the
I2C/SMBus interface. Monitoring parameters can also be
pre-configured to provide alerts for specific conditions. See
Application Note AN2033 for more details on SMBus monitoring.
Multi-mode Pins
In order to simplify circuit design, the ZL2106 incorporates
patented multi-mode pins that allow the user to easily configure
many aspects of the device without programming. Most power
management features can be configured using these pins. The
multi-mode pins can respond to four different connections, as
shown in Table 1. These pins are sampled when power is applied
or by issuing a PMBus Restore command (See Application Note
AN2033).
PIN-STRAP SETTINGS
This is the simplest method, as no additional components are
required. Using this method, each pin can take on one of three
possible states: LOW, OPEN, or HIGH. These pins can be
connected to the V2P5 pin for logic HIGH settings as this pin
provides a regulated voltage higher than 2V. Using a single pin
one of three settings can be selected.
TABLE 1. MULTI-MODE PIN CONFIGURATION
PIN TIED TO
VALUE
LOW
(Logic LOW)
< 0.8VDC
OPEN
(N/C)
HIGH
(Logic HIGH)
Resistor to SGND
No connection
> 2.0VDC
Set by resistor value
11 FN6852.6
February 20, 2013
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ZL2106.PDF ] | |
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