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ZL2005 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ZL2005
Beschreibung Digital-DC Integrated Power Management and Conversion IC
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 30 Seiten
ZL2005 Datasheet, Funktion
Data Sheet
ZL2005
www.DataSheet4U.com
February 18, 2009
FN6848.0
Digital-DC™ Integrated Power Management and Conversion IC
Description
The ZL2005 is an innovative mixed-signal power
management and conversion IC that combines a com-
pact, efficient, synchronous DC/DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs’ Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple, low-voltage power
domains on a single PCB.
The ZL2005 is designed to be a flexible building block
for DC power and can be easily adapted to designs
ranging from a single-phase power supply operating
from a 3.3 V input to a multi-phase supply operating
from a 12 V input. The ZL2005 eliminates the need
for complicated power supply managers as well as
numerous external discrete components.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005 uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
Features
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Power good/enable
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I2C/SMBus communication
• Output overvoltage and overcurrent protection
• PMBus compliant
Power Conversion
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.6 V to 5.5 V output range
• ± 1% output accuracy
• Internal 3 A drivers support >30 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
• Point of load converters
V (0,1)
SS (0,1)
VTRK
MGN
SYNC
SCL
SDA
SALRT
POWER
MANAGEMENT
LDO
NON-
VOLATILE
MEMORY
I2 C
PWM
CONTROLLER
MONITOR
ADC
DRIVER
CURRENT
SENSE
TEMP
SENSOR
BST
GH
SW
GL
ISENA
ISENB
SA (0,1)
VTRK VSEN
TACH XTEMP PGND SGND DGND
Figure 1. Block Diagram
Figure 2. Efficiency vs. Load Current
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






ZL2005 Datasheet, Funktion
ZL2005
Table 3. Electrical Specifications
www.DataSheet4U.com
Unless otherwise specified VDD = 12 V, TA = -40oC to +85oC. Typical values are at TA = 25oC. (Continued)
Parameter
Condition
Min Typ Max Unit
Gate Drivers
High-side driver voltage
(VBST - VSW)
High-side driver peak gate drive
current (pull down)
(VBST - VSW) = 4.5 V
– 4.5 – V
2 3 –A
High-side driver pull-up resistance
High-side driver pull-down
resistance
Low-side driver peak gate drive
current (pull-up)
(VBST - VSW) = 4.5 V,
(VBST - VGH) = 50 mV
(VBST - VSW) = 4.5 V,
(VGH - VSW) = 50 mV
VR = 5 V
– 0.8 2 Ω
– 0.5 2 Ω
– 2.5 – A
Low-side driver peak gate drive
current (pull-down)
VR = 5 V
– 1.8 – A
Low-side driver pull-up resistance
Low-side driver pull-down
resistance
Switching timing
VR = 5 V,
(VR - VGL) = 50 mV
VR = 5 V,
(VGL - PGND) = 50 mV
– 1.2 2 Ω
– 0.5 2 Ω
GH rise and fall time
GL rise and fall time
Tracking
(VBST - VSW) = 4.5 V,
CLOAD = 2.2 nF
VR = 5 V,
CLOAD = 2.2 nF
– 5 20 ns
– 5 20 ns
VTRK input bias current
VTRK = 5.5 V
– 110 200 µA
VTRK tracking threshold
VTRK >= 0.3 V
– 100
+ 100 mV
6 FN6848.0
February 18, 2009

6 Page









ZL2005 pdf, datenblatt
4.2 Power Conversion Overview
ZL2005
www.DataSheet4U.com
TACH
VTRK
SYNC
{SALRT
SMBUS SDA
SCL
SA(0,1)
INPUT VOLTAGE BUS
PG EN MGN ILIM(0,1) SS(0,1) DLY(0,1) V(0,1) FC(0,1)
VDD
POWER MANAGEMENT
SYNC
GEN
DIGITAL
COMPENSATOR
PLL
REFCN
DAC
ADC
D-PWM
NLR
ADC
COMMUNICATION
ADC
MUX
VR LDO VR
BST
MOSFET
DRIVERS
GH
SW
GL
- VSEN
Σ
+
VDD
TEMP
SENSOR
ISENB
ISENA
VSEN
XTEMP
VOUT
Figure 5. ZL2005 Detailed Block Diagram
The ZL2005 operates as a voltage-mode, synchronous
buck converter with a selectable, constant frequency
Pulse Width Modulator (PWM) control scheme that
uses external MOSFETs, inductor and capacitors to
perform power conversion.
Figure 6 illustrates the basic synchronous buck con-
verter topology showing the primary power train com-
ponents. This converter is also called a step-down
converter, as the output voltage must always be lower
than the input voltage.
VR BST
GH
ZL2005 SW
VIN
DB
QH
CB L1
GL QL
CIN
VOUT
COUT
In its most simple configuration, the ZL2005 requires
two external N-channel power MOSFETs, one for the
top control MOSFET (QH) and one for the bottom
synchronous MOSFET (QL). The amount of time that
QH is on as a fraction of the total switching period is
known as the duty cycle D, which is described by the
following equation:
D V-----O----U----T--
VIN
Figure 6. Synchronous Buck Converter
12 FN6848.0
February 18, 2009

12 Page





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