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PDF LPC2365 Data sheet ( Hoja de datos )
| Número de pieza | LPC2365 | |
| Descripción | Single-chip 16-bit/32-bit microcontrollers | |
| Fabricantes | NXP Semiconductors | |
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LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash
with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 7.1 — 16 October 2013
Product data sheet
1. General description
The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation that combines the microcontroller with up to 512 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.
They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed
device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels
(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three
I2C-bus interfaces, and an I2S-bus interface. This blend of serial communications
interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB
SRAM for Ethernet, 8 kB SRAM for USB and general purpose use, together with 2 kB
battery powered SRAM make these devices very well suited for communication gateways
and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one
PWM unit, a CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up
to 12 edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB SRAM for general purpose DMA use also accessible by the USB.
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip flash with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card
port, as well as for memory-to-memory transfers.
1 page  
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
5. Block diagram
P0, P1, P2,
P3, P4
TMS TDI trace signals
TRST TCK TDO
EXTIN0
XTAL1
XTAL2
VDDA
RESET
VDD(3V3)
LPC2364/65/66/67/68
128/256/
8/32 kB 512 kB
SRAM FLASH
TEST/DEBUG
INTERFACE
HIGH-SPEED
GPI/O
70 PINS
TOTAL
INTERNAL
CONTROLLERS
SRAM FLASH
ARM7TDMI-S
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
VECTORED
INTERRUPT
CONTROLLER
AHB2
AHB
BRIDGE
AHB
BRIDGE
AHB1
RMII(8)
EINT3 to EINT0
P0, P2
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
PWM1
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA(2)
GP DMA
CONTROLLER
I2S INTERFACE
SPI, SSP0 INTERFACE
P0, P1
LEGACY GPI/O
52 PINS TOTAL
SSP1 INTERFACE
6 × AD0
A/D CONVERTER
AOUT
D/A CONVERTER
VBAT
ppoowweerr ddoommaaiinn 22
RTCX1
RTCX2
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SD/MMC CARD
INTERFACE(1)
UART0, UART2, UART3
UART1
CAN1, CAN2(2)
SYSTEM CONTROL
I2C0, I2C1, I2C2
VREF
VSSA, VSS
VDD(DCDC)(3V3)
VBUS
USB_D+, USB_D−
USB_CONNECT
USB_UP_LED
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
(1) LPC2367/68 only.
(2) LPC2364/66/68 only.
Fig 1. LPC2364/65/66/67/68 block diagram
002aac566
LPC2364_65_66_67_68
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 16 October 2013
© NXP B.V. 2013. All rights reserved.
5 of 69
5 Page 
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
Table 4. Pin description …continued
Symbol
Pin Ball Type
P0[9]/
I2STX_SDA/
MOSI1/MAT2[3]
76[1]
A10[1]
I/O
I/O
P0[10]/TXD2/
SDA2/MAT3[0]
48[1]
P0[11]/RXD2/
SCL2/MAT3[1]
49[1]
P0[15]/TXD1/
SCK0/SCK
62[1]
P0[16]/RXD1/
SSEL0/SSEL
63[1]
P0[17]/CTS1/
MISO0/MISO
61[1]
P0[18]/DCD1/
MOSI0/MOSI
60[1]
P0[19]/DSR1/
MCICLK/SDA1
59[1]
P0[20]/DTR1/
58[1]
MCICMD/SCL1
H7[1]
K9[1]
F10[1]
F8[1]
F9[1]
F6[1]
G10[1]
G9[1]
I/O
O
I/O
O
I/O
O
I/O
I
I/O
O
I/O
O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I
O
I/O
I/O
O
I
I/O
Description
P0[9] — General purpose digital input/output pin.
I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
MOSI1 — Master Out Slave In for SSP1.
MAT2[3] — Match output for Timer 2, channel 3.
P0[10] — General purpose digital input/output pin.
TXD2 — Transmitter output for UART2.
SDA2 — I2C2 data input/output (this is not an open-drain pin).
MAT3[0] — Match output for Timer 3, channel 0.
P0[11] — General purpose digital input/output pin.
RXD2 — Receiver input for UART2.
SCL2 — I2C2 clock input/output (this is not an open-drain pin).
MAT3[1] — Match output for Timer 3, channel 1.
P0[15] — General purpose digital input/output pin.
TXD1 — Transmitter output for UART1.
SCK0 — Serial clock for SSP0.
SCK — Serial clock for SPI.
P0[16] — General purpose digital input/output pin.
RXD1 — Receiver input for UART1.
SSEL0 — Slave Select for SSP0.
SSEL — Slave Select for SPI.
P0[17] — General purpose digital input/output pin.
CTS1 — Clear to Send input for UART1.
MISO0 — Master In Slave Out for SSP0.
MISO — Master In Slave Out for SPI.
P0[18] — General purpose digital input/output pin.
DCD1 — Data Carrier Detect input for UART1.
MOSI0 — Master Out Slave In for SSP0.
MOSI — Master Out Slave In for SPI.
P0[19] — General purpose digital input/output pin.
DSR1 — Data Set Ready input for UART1.
MCICLK — Clock output line for SD/MMC interface. (LPC2367/68 only)
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[20] — General purpose digital input/output pin.
DTR1 — Data Terminal Ready output for UART1.
MCICMD — Command line for SD/MMC interface. (LPC2367/68 only)
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
LPC2364_65_66_67_68
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 16 October 2013
© NXP B.V. 2013. All rights reserved.
11 of 69
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC2365.PDF ] | |
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