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PDF CY7C1371D Data sheet ( Hoja de datos )
| Número de pieza | CY7C1371D | |
| Descripción | 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1371D
CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
■ 3.3 V/2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 119-ball BGA, and 165-ball FBGA packages
■ Three chip enables for simple depth expansion
■ Automatic power-down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18
synchronous flow through burst SRAM designed specifically to
support unlimited true back-to-back read/write operations with
no wait state insertion. The CY7C1371D/CY7C1373D is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Errata: For information on silicon errata, see Errata on page 36. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05556 Rev. *R
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 19, 2015
1 page  
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
CY7C1371D
CY7C1371D
CY7C1373D
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSS
75
74
DQB
DQB
BYTE B
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57
DQA
BYTE A
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 DQPA
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 36.
Document Number: 38-05556 Rev. *R
Page 5 of 40
5 Page 
CY7C1371D
CY7C1373D
Functional Overview
The CY7C1371D/CY7C1373D is a synchronous flow through
burst SRAM designed specifically to eliminate wait states during
write-read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. Maximum access delay from the clock rise (tCDV) is
6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■ CEN is asserted LOW
■ CE1, CE2, and CE3 are all asserted active
■ The write enable input signal WE is deasserted HIGH
■ ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tristated immediately.
Burst Read Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Accesses section above. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wraps around
when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1371D/CY7C1373D provides byte write
capability that is described in the truth table. Asserting the write
enable input (WE) with the selected byte write select input
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remains unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included to
greatly simplify read/modify/write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1371D/CY7C1373D is a common I/O device,
data must not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQPX inputs. Doing so tristates
the output drivers. As a safety precaution, DQs and DQPX are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW to load the initial address,
as described in the Single Write Accesses section above. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BWX inputs must be
driven in each cycle of the burst write, to write the correct bytes
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Document Number: 38-05556 Rev. *R
Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1371D.PDF ] | |
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