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PDF LC72144M Data sheet ( Hoja de datos )
| Número de pieza | LC72144M | |
| Descripción | PLL Frequency Synthesizer | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN5377B
CMOS LSI
LC72144M
PLL Frequency Synthesizer
Overview
The LC72144M is an electronic tuning PLL frequency
synthesizer for use in car and home products, and allows
high-performance multifunction tuners to be implemented
easily, since it includes an A/D converter, a high-speed
lockup circuit, and a crystal oscillator circuit that support
AM up-conversion.
Features
• High-speed programmable dividers for
— 10 to 160 MHz on FMIN using pulse swallower
— 0.5 to 40.0 MHz on AMIN using pulse swallower
and direct division
• General-purpose counters
— HCTR for 0.4 to 25.0 MHz frequency measurement
— LCTR for 10 to 500 kHz frequency measurement
and 4.0 Hz to 20 × 103 Hz period measurement
• 4.5, 7.2, 10.25 or 10.35 MHz crystal
• Twelve selectable reference frequencies (1, 3*2, 5, 9*2,
10, 3.125, 6.25, 12.5, 25, 30*2, 50 and 100*1 kHz)
Note: 1. Not supported when a 10.35 or 10.25 MHz
crystal oscillator is used.
2. Not supported when a 10.25 MHz crystal
oscillator is used.
• Phase comparator
— Insensitive band control
— Unlock detection
— Sub-charge pump for high-speed locking
— Deadlock clear circuit
• A/D converter: 6 bits, 2 inputs
• Serial data input and output
Supports control and communication in the CCB format
• Power-on reset circuit
• On-chip crystal oscillator output buffer
• Inputs/outputs (using six general-purpose input/output
ports)
• Operating ranges
— Power-supply voltage: 4.5 to 5.5 V
— Operating temperature: –40 to 85°C
• Package: MFP24S
Package Dimensions
unit: mm
3112-MFP24S
[LC72144M]
SANYO: MFP24S
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
82097HA (OT)/N3096HA (OT)/73096HA (OT) No. 5377-1/22
1 page  
LC72144M
Continued from preceding page.
Parameter
High-level 3-state off
leakage current
Low-level 3-state off
leakage current
Input capacitance
A/D converter linearity error
Pull-down transistor on resistance
Current drain
Symbol
IOFFH
IOFFL
CIN
Err
Rpd1
Rpd2
IDD1
IDD2
IDD3
Conditions
PD0, PD1, PDS: VO = VDD
PD0, PD1, PDS: VO = 0 V
FMIN
ADC0, ADC1
FMIN
AMIN
VDD: Xtal = 10.35 MHz, fIN2 = 160 MHz,
VIN2 = 70 mVrms, fIN4 = 25 MHz, VIN4 = 40 mVrms
VDD: PLL block stopped (PLL INHIBIT),
Xtal oscillator operating (Xtal = 10.35 MHz)
VDD: PLL block stopped, Xtal oscillator stopped
min
–0.5
80
80
typ
0.01
0.01
6
200
200
10
0.5
max
200
200
+0.5
600
600
15
1.5
10
Unit
nA
nA
pF
LSB
kΩ
kΩ
mA
mA
µA
Serial Data Timing
Internal
data
latching
When CL is stopped at the low level
Old New
Internal
data
latching
When CL is stopped at the high level
Old New
No. 5377-5/22
5 Page 
LC72144M
Continued from preceding page.
Control section/
No. data
Function
Data that determines the DO and I/O-5 pin outputs
ULD DT1 DT0
DO
0 0 0 Low when unlocked
0 0 1 end-AD
0 1 0 end-UC
0 1 1 IN*1
1 0 0 Open
1 0 1 end-AD
1 1 0 end-UC
1 1 1 IN*1
Note: end-AD: A/D converter conversion completion
end-UC: General-purpose counter conversion completion
Control data for
the DO and
(4) I/O-5 pins
ULD, DT0,
DT1, IL0, IL1
Start
Finish CE: High
(I-1 charge)
I/O-5
OUT5 flag*2
Low when unlocked*2
Related data
OUT5
I/O-1, I/O-2, I/O-5
Note: 1.
IL1 IL0
IN state
0 0 Open
0 1 I-1 (pin state)
1 0 I-2 (pin state)
1 1 DO goes low when I-1 changes.
Note: 2. However, this pin becomes open if the I/O-1 and I/O-2 pins are specified to be output ports.
Note: 2. Invalid if the I/O-5 pin is specified to be an input port.
Note: Cannot be used when the crystal oscillator is stopped. (The DO pin will not change state.)
(Reference divider: When R3 = R2 = R1 = 1, and R0 = 0)
A/D converter conversion start data
ADS = 1: Resets and starts the A/D converter
= 0: Resets the A/D converter
A/D converter
control data
(5)
ADS, ADI0,
ADI1
ADI1
1
1
0
0
ADI0
1
0
1
0
Stopped
ADC0
ADC1
ADC0, ADC1
AD input pin
If ADC0 and ADC1 are specified for AD input at the same time, conversions are performed in the order
ADC0 first, then ADC1.
See the item on the structure of the A/D converter for details.
Continued on next page.
No. 5377-11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LC72144M.PDF ] | |
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