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LC72136NM Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC72136NM
Beschreibung PLL Frequency Synthesizer for Electronic Tuning
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 23 Seiten
LC72136NM Datasheet, Funktion
Ordering number : EN5608
CMOS LSI
LC72136N, 72136NM
PLL Frequency Synthesizer
for Electronic Tuning
Overview
The LC72136N and LC72136NM are PLL frequency
synthesizers for use in radio/cassette players. They allow
high-performance AM/FM tuners to be implemented
easily.
Features
• High-speed programmable frequency divider
— FMIN: 10 to 160 MHz.....Pulse swallower
(divide-by-two prescaler built in)
— AMIN: 2 to 40 MHz.........Pulse swallower
0.5 to 10 MHz......Direct division
• IF counter
IFIN: 0.4 to 12 MHz................For use as an AM/FM IF
counter
• Reference frequency
— Selectable from one of eight frequencies (crystal
oscillator: 75 kHz)
1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz
• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 6
— I/O ports: 2
— Supports clock time base output
• Serial Data I/O
— Supports CCB format communication with the
system controller.
• Operating ranges
— Supply voltage: 4.5 to 5.5 V
— Operating temperature: –20 to +70°C
• Packages
—DIP22S/MFP24S
Package Dimensions
unit: mm
3059-DIP22S
[LC72136N]
unit: mm
3112-MFP24S
[LC72136NM]
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO: DIP22S
SANYO: MFP24S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N3096HA (OT) No. 5608-1/23






LC72136NM Datasheet, Funktion
Pin Functions
Symbol
Pin No.
(MFP pin numbers
are in parentheses.)
Type
XIN
XOUT
22 (24)
1 (1)
Xtal
LC72136N, 72136NM
Functions
• Crystal oscillator connections (75 kHz)
• The extremely high input impedance of the XIN pins
means that applications must take the possibility of
leakage into account.
Circuit configuration
FMIN
16 (17)
Local oscillator
signal input
• FMIN is selected when the serial data input DVS bit is
set to 1.
• The input frequency range is from 10 to 160 MHz.
• The input signal passes through the internal divide-by-
two prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
AMIN
15 (16)
Local oscillator
signal input
• AMIN is selected when the serial data input DVS bit is
set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
CE
3 (4)
Chip enable
• Set this pin high when inputting (DI) or outputting (DO)
serial data.
CL
5 (6)
Clock
• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
DI
4 (5)
Input data
• Inputs serial data transferred from the controller to the
LC72136N.
• Outputs serial data transferred from the LC72136N to
DO
6 (7)
Output data
the controller. The data output is determined by the
DOC0 to DOC2 bits in the serial data.
• The LC72136N power supply pin. (VDD = 4.5 to 5.5 V)
VDD
17 (18)
Power supply
• The power on reset circuit operates when power is first
applied.
VSS
21 (22)
Ground
• The LC72136N ground
Continued on next page.
No. 5608-6/23

6 Page









LC72136NM pdf, datenblatt
LC72136N, 72136NM
Continued from preceding page.
No. Control block/data
IF counter control data
(11) IFS
LSI test data
TEST 0 to TEST3
(12)
Description
• This data should be set to 1 in normal operation. Setting this data to 0 switches
the LC72136N to a reduced input sensitivity mode in which the sensitivity is reduced by
10 to 30 mVrms.
* See the “IF Counter Operation” item for details.
• LSI test data
TEST0
TEST1 All three bits must be set to 0.
TEST2
All the test data is set to 0 following a power-on reset.
DO Output Data (Serial Data Output) Structure
3. OUT mode
Related data
DO Output Data
No. Control block/data
I/O port data
I2, I1
(1)
PLL unlock data
(2) UL
IF counter binary data
(3) C19 to C0
Description
• Data latched from the states of the I/O ports, pins IO1 and IO2.
This data reflects the pin states, regardless of whether they are in input or output mode.
The data is latched when OUT mode is selected.
I1 IO1 pin state High: 1
I2 IO2 pin state Low: 0
• Data latched from the state of the unlock detection circuit
UL 0: Unlocked
UL 1: Locked or in detection stopped mode
• Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19 Binary counter MSB
C0 Binary counter LSB
Related data
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
No. 5608-12/23

12 Page





SeitenGesamt 23 Seiten
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