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LC72131 Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC72131
Beschreibung AM/FM PLL Frequency Synthesizer
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 23 Seiten
LC72131 Datasheet, Funktion
Ordering number : EN4921B
CMOS LSI
LC72131, 72131M
AM/FM PLL Frequency Synthesizer
Overview
The LC72131 and LC72131M are PLL frequency
synthesizers for use in tuners in radio/cassette players.
They allow high-performance AM/FM tuners to be
implemented easily.
Applications
Package Dimensions
unit: mm
3059-DIP22S
[LC72131]
PLL frequency synthesizer
Functions
• High speed programmable dividers
— FMIN: 10 to 160 MHz ..........pulse swallower
(built-in divide-by-two prescaler)
— AMIN: 2 to 40 MHz ..............pulse swallower
0.5 to 10 MHz ...........direct division
• IF counter
— IFIN: 0.4 to 12 MHz ...........AM/FM IF counter
• Reference frequencies
— Twelve selectable frequencies
(4.5 or 7.2 MHz crystal)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 kHz
• Phase comparator
— Dead zone control
— Unlock detection circuit
— Deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— Input or output ports: 2
— Support clock time base output
• Serial data I/O
— Support CCB format communication with the
system controller.
• Operating ranges
— Supply voltage........................4.5 to 5.5 V
— Operating temperature............–40 to +85°C
• Packages
— DIP22S/MFP20
unit: mm
3036B-MFP20
[LC72131M]
SANYO: DIP22S
SANYO: MFP20
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
62096HA (OT)/O3195HA (OT)/92294TH (OT) No. 4921-1/23






LC72131 Datasheet, Funktion
Pin Functions
Symbol
Pin No.
(MFP pin Nos. are
in parentheses.)
Type
LC72131, 72131M
Functions
XIN
XOUT
1 (1)
22 (20)
Xtal OSC
• Crystal resonator connection
(4.5/7.2 MHz)
Circuit configuration
FMIN
16 (14)
Local oscillator
signal input
• FMIN is selected when the serial data input DVS bit is
set to 1.
• The input frequency range is from 10 to 160 MHz.
• The input signal passes through the internal divide-by-
two prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
AMIN
15 (13)
Local oscillator
signal input
• AMIN is selected when the serial data input DVS bit is
set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
CE
3 (2)
Chip enable
Set this pin high when inputting (DI) or outputting (DO)
serial data.
CL
5 (4)
Clock
• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
DI
4 (3)
Data input
• Inputs serial data transferred from the controller to the
LC72131.
• Outputs serial data transferred from the LC72131 to the
DO
6 (5)
Data output
controller.
The content of the output data is determined by the
serial data DOC0 to DOC2.
• The LC72131 power supply pin (VDD = 4.5 to 5.5 V)
VDD
17 (15)
Power supply
• The power on reset circuit operates when power is first
applied.
Continued on next page.
No. 4921-6/23

6 Page









LC72131 pdf, datenblatt
LC72131, 72131M
Continued from preceding page.
No. Control block/data
IF counter control data
(11) IFS
LSI test data
TEST 0 to TEST3
(12)
(13) DNC
Functions
• This data must be set 1 in normal mode.
Though if this value is set to zero, the system enters input sensitivity degradation mode,
and the sensitivity is reduced to 10 to 30 mVrms.
* See the “IF Counter Operation” item for details.
• LSI test data
TEST0
TEST1 These values must all be set to 0.
TEST2
These test data are set to 0 automatically after the power-on reset.
Don’t care. This data must be set to 0.
Related data
3. DO Output Data (Serial Data Output)
• OUT Mode
No. Control block/data
I/O port data
I2, I1
(1)
PLL unlock data
(2) UL
IF counter binary data
(3) C19 to C0
4. DO Output Data
Functions
• Latched from the pin states of the IO1 and IO2 I/O ports.
• These values follow the pin states regardless of the input or output setting.
• Bits I2, I1 reflect the data latched into each input port when the device changes to OUT Mode.
I1 IO1 pin state High: 1
I2 IO2 pin state Low: 0
• Latched from the state of the unlock detection circuit.
UL 0: Unlocked
UL 1: Locked or detection stopped mode
• Latched from the value of the IF counter (20-bit binary counter).
C19 MSB of the binary counter
C0 LSB of the binary counter
Related data
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
No. 4921-12/23

12 Page





SeitenGesamt 23 Seiten
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