PDF MT54W4MH8B Data sheet ( Hoja de datos )

Número de pieza	MT54W4MH8B
Descripción	SRAM 2-WORD BURST
Fabricantes	Micron Technology
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ADVANCE‡ 4 MEG x 8, 4 MEG x 9, 2 MEG x 18w, w1w.DMataESGheext4U3.co6m 1.8V VDD, HSTL, QDRIIb2 SRAM 36Mb QDR™II SRAM 2-WORD BURST MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B FEATURES • DLL circuitry for accurate output data placement • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE operation • Fast clock to valid data times • Full data coherency, providing most current data • Two-tick burst counter for low DDR transaction size • Double data rate operation on read and write ports • Two input clocks (K and K#) for precise DDR timing at clock rising edges only • Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device • Single address bus • Simple control logic for easy depth expansion • Internally self-timed, registered writes • +1.8V core and HSTL I/O • Clock-stop capability • 15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package • User-programmable impedance output • JTAG boundary scan OPTIONS MARKING1 • Clock Cycle Timing 4ns (250 MHz) 5ns (200 MHz) 6ns (167 MHz) 7.5ns (133 MHz) • Configurations 4 Meg x 8 4 Meg x 9 2 Meg x 18 1 Meg x 36 • Package 165-ball, 15mm x 17mm FBGA -4 -5 -6 -7.5 MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B F NOTE: 1. A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/number- guide. Figure 1 165-Ball FBGA VALID PART NUMBERS PART NUMBER MT54W4MH8BF-xx MT54W4MH9BF-xx MT54W2MH18BF-xx MT54W1MH36BF-xx DESCRIPTION 4 Meg x 8, QDRIIb2 FBGA 4 Meg x 9, QDRIIb2 FBGA 2 Meg x 18, QDRIIb2 FBGA 1 Meg x 36, QDRIIb2 FBGA GENERAL DESCRIPTION The Micron® QDR™II (Quad Data Rate™) synchro- nous, pipelined burst SRAM employs high-speed, low- power CMOS designs using an advanced 6T CMOS process. The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respec- tively. Each address location is associated with two words that burst sequentially into or out of the device. 36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev. 9/02 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. ‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 1 page ADVANCE 4 MEG x 8, 4 MEG x 9, 2 MEG x 18w, w1w.DMataESGheext4U3.co6m 1.8V VDD, HSTL, QDRIIb2 SRAM 4 MEG x 8 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA 12 3 A CQ# VSS/SA1 SA B NC NC NC C NC NC NC D NC D4 NC E NC NC Q4 F NC NC NC G NC D5 Q5 H DLL# VREF VDDQ J NC NC NC K NC NC NC L NC Q6 D6 M NC NC NC N NC D7 NC P NC NC Q7 R TDO TCK SA NOTE: 1. Expansion address: 2A for 72Mb 2. NW1# controls writes to D4:D7 3. Expansion address: 7A for 144Mb 4. Expansion address: 5B for 288Mb 5. NW0# controls writes to D0:D3 4 W# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1#2 NC/SA4 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K# K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C# 7 NC/SA3 NW0#5 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI 36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 5 Page ADVANCE 4 MEG x 8, 4 MEG x 9, 2 MEG x 18w, w1w.DMataESGheext4U3.co6m 1.8V VDD, HSTL, QDRIIb2 SRAM Figure 4 Bus Cycle State Diagram RD LOAD NEW READ ADDRESS RD always READ DOUBLE /RD WT LOAD NEW WRITE ADDRESS AT K#↑ WT always WRITE DOUBLE AT K#↑ READ PORT NOP R_Init=0 /RD Supply voltage provided POWER-UP Supply voltage provided WRITE PORT NOP /WT /WT NOTE: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx . . . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. State transitions: RD = (R# = LOW); WT = (W# = LOW). 3. Read and write state machines can be simultaneously active. 4. State machine control timing sequence is controlled by K. 36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 11 Page

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