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ORSO82G5 Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer ORSO82G5
Beschreibung (ORSO42G5 / ORSO82G5) 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
Hersteller Lattice Semiconductor
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ORSO82G5 Datasheet, Funktion
ORCA® ORSO42G5 and ORSO82G5www.DataSheet4U.com
0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
July 2008
Data Sheet DS1028
Introduction
Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5
devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and
ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbps and 20 Gbps respectively.
These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non-
SONET applications. The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6-
2.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable
FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already
been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces.
With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design-
ers can build a configurable interface using proven backplane driver/receiver technology. Designers can also use
the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The
ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbps backplane data connection and, with the
ORSO82G5, support both work and protection connections between a line card and switch fabric.
The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a
board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system
performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network
designers will benefit from using the backplane transceiver as a network termination device. Sister devices, the
ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet
(XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling,
streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi-
nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes
them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET
applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The
ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic
Device
PFU
FPGA Max
PFU Rows Columns Total PFUs User I/O
LUTs
EBR
Blocks2
EBR Bits
(K)
FPGA
System
Gates (K)1
ORSO42G5
36
36
1296
204 10,368 12
111 333-643
ORSO82G5
36
36
1296
372 10,368 12
111 333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with
40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 4 PLLs.
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1028_08.0






ORSO82G5 Datasheet, Funktion
Lattice Semiconductor
ORCA ORSO42G5 and ORSOw8w2wG.D5atDaSahteaetS4Uh.ceoemt
setup/hold and clock to out performance.
• New Double-Data Rate (DDR) and zero-bus turn-around (ZBT) memory interfaces support the latest high-speed
memory interfaces.
• New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal
logic.
• ispLEVER™ development system software. Supported by industry-standard CAE tools for design entry, synthe-
sis, simulation, and timing analysis.
• Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) levels 1, 2, and 3; as well as POS-PHY3.
Description
What Is an FPSC?
FPSCs, or Field-Programmable System Chips, are devices that combine field-programmable logic with ASIC or
mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the
design effort savings of using soft Intellectual Property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice’s Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
Programmable Logic Cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the
FPGA functionality is changed—all of the Series 4 FPGA capability is retained: Embedded Block RAMs, MPI,
PCMs, boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing
pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins
retain their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
ORCA Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-
master 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA
logic functions including the Embedded Block RAMs and the MicroProcessor Interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This
supports user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embed-
ded core configurations may be designed into a single device with user-programmable control over which configu-
rations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
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ORSO82G5 pdf, datenblatt
Lattice Semiconductor
ORCA ORSO42G5 and ORSOw8w2wG.D5atDaSahteaetS4Uh.ceoemt
• Support for OC-48 and OC-192 (in block OC-48) formats.
• SONET framing, scrambling and SONET Mode channel alignment.
• Performance monitoring functions such as Bit Interleaved Parity (BIP-8) generation and checking and Out-Of-
Frame (OOF) and Remote Defect Indication (RDI-L) detection.
• Cell Mode cell creation and extraction, idle cell insertion/deletion, destriping and striping functions.
• Additionally, there are two independent memory blocks in the core. Each embedded RAM block has a capacity of
4K words by 36 bits.
The ORSO42G5 and ORSO82G5 embedded cores contain, respectively, four-channel and eight-channel clock and
data recovery macrocells and logical blocks performing functions such as SONET framing, scrambling/descram-
bling and cell processing. The channels each operate from 0.6 to 2.7 Gbps with per channel CDR functionality. The
CDR interface enables high-speed asynchronous serial data transfer between system devices. Devices can be on
the same PC-board, on separate boards connected across a backplane, or connected by cables. Figure 2 shows a
top level block diagram of the backplane driver logic in the embedded core (embedded RAM not shown).
Figure 2. Top Level Block Diagram ORSO42G5 and ORSO82G5 Embedded Cores
User
Receive (RX) Path
ORCA 4E04
FPGA Logic
Cell
Processing
Psuedo-
SONET
Processing
Transmit (TX) Path
I/O
ORSO42G5 and ORSO82G5 Main Operating Modes - Overview
The ORSO42G5 and ORSO82G5 support four and eight 0.6 to 2.7 Gbps serial data channels respectively, which
can operate independently or can be combined together (aligned) to achieve higher bit rates. The mode of opera-
tion of the core is defined by a set of control registers, which can be written through the system bus interface. The
status of the core is stored in a set of status registers, which can be read through the system bus interface.
The serial data channels support OC-48 rates on each channel. The standard OC-48 rate, 2.488 Gbits, is used as
the nominal data rate for the technical discussions that follow. OC-192 is also supported but is transmitted and
received in block OC-48 links. The scrambled data stream conforms to the GR-255 specified polynomial sequence
of 1+x6+x7.
There are three main operating modes in the ORSO42G5 and ORSO82G5 as described below:
• SERDES only (bypass) mode
• SONET mode
• Cell mode
– Two-link sub-mode
– Eight-link sub-mode (ORSO82G5 only)
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