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PDF MCP14628 Data sheet ( Hoja de datos )
| Número de pieza | MCP14628 | |
| Descripción | 2A Synchronous Buck Power MOSFET Driver | |
| Fabricantes | Microchip Technology | |
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MCP14628
2A Synchronous Buck Power MOSFET Driver
Features
• Dual Output MOSFET Driver for Synchronous
Applications
• High Peak Output Current: 2A (typical)
• Adaptive Cross Conduction Protection
• Internal Bootstrap Blocking Device
• +36V BOOT Pin Maximum Rating
• Enhanced Light Load Efficiency Mode
• Low Supply Current: 80 µA (typical)
• High Capacitive Load Drive Capability:
- 3300 pF in 10 ns (typical)
• Tri-State PWM Pin for Power Stage Shutdown
• Input Voltage Undervoltage Lockout Protection
• Space Saving Packages:
- 8-Lead SOIC
- 8-Lead 3x3 DFN
Applications
• High Efficient Synchronous DC/DC Buck
Converters
• High Current Low Output Voltage Synchronous
DC/DC Buck Converters
• High Input Voltage Synchronous DC/DC Buck
Converters
www.DataShee•t4CUo.croemVoltage Supplies for Microprocessors
General Description
The MCP14628 is a dual MOSFET gate driver
designed to optimally drive two N-Channel MOSFETs
arranged in a non-isolated synchronous buck converter
topology. With the capability to source 2A peaks
typically from both the high-side and low-side drives,
the MCP14628 is an ideal companion to buck control-
lers that lack integrated gate drivers. Additionally,
greater design flexibility is offered by allowing the gate
drivers to be placed close to the power MOSFETs.
The MCP14628 features the capability to sink 3.5A
peak typically for the low-side gate drive. This allows
the MCP14628 the capability of holding off the low-side
power MOSFET during the rising edge of the PHASE
node. Internal adaptive cross conduction protection
circuitry is also used to mitigate both external power
MOSFETs from simultaneously conducting.
The low resistance pull-up and pull-down drives allow
the MCP14628 to quickly transition a 3300 pF load in
typically 10 ns and with a propagation time of typically
20 ns. Bootstrapping for the high-side drive is internally
implemented which allows for a reduced system cost
and design complexity.
The PWM input to the MCP14628 can be tri-stated to
force both drive outputs low for true power stage
shutdown. Light load system efficiency is improved by
using the diode emulation feature of the MCP14628.
When the FCCM pin is grounded, diode emulation
mode is entered. In this mode, discontinuous conduc-
tion is allowed by sensing when the inductor current
reach zero and turning off the low-side power
MOSFET.
Package Types
8-Lead SOIC
8-Lead DFN
HIGHDR
BOOT
PWM
GND
1
2
3
4
8 PHASE
7 FCCM
6 VCC
5 LOWDR
HIGHDR
BOOT
PWM
GND
1
2
3
4
8 PHASE
7 FCCM
6 VCC
5 LOWDR
Note 1: Exposed pad on the DFN is electrically isolated.
© 2008 Microchip Technology Inc.
DS22083A-page 1
1 page  
MCP14628
2.0 TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C with VCC = 5.0V.
25
tRH
20
15 tRL
10
5
0
0 1500 3000 4500 6000 7500
Capacitive Load (pF)
FIGURE 2-1:
Load.
Rise Times vs. Capacitive
25
20 tFH
15
10
tFL
5
0
0 1500 3000 4500 6000 7500
Capacitive Load (pF)
FIGURE 2-4:
Load.
Fall Times vs. Capacitive
14
13 CLOAD = 3,300 pF
12
tRH
11
10 tFH
9
8
7
6
-40 -25 -10 5 20 35 50 65 80 95 110 125
www.DataSheet4U.com
Temperature (°C)
FIGURE 2-2:
HIGHDR Rise and Fall Time
vs. Temperature.
24
22 CLOAD = 3,300 pF
20
18
tPDHH
16
tPDLH
14
12
10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-3:
HIGHDR Propagation Delay
vs. Temperature.
12
11 CLOAD = 3,300 pF
10 tRL
9
8
7
6
5 tFL
4
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-5:
LOWDR Rise and Fall Time
vs. Temperature.
30
28 CLOAD = 3,300 pF
26
24
22 tPDHL
20
18
16 tPDLL
14
12
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-6:
LOWDR Propagation Delay
vs. Temperature.
© 2008 Microchip Technology Inc.
DS22083A-page 5
5 Page 
5.0 APPLICATION INFORMATION
5.1 Bootstrap Capacitor Select
The selection of the bootstrap capacitor is based upon
the total gate charge of the high-side power MOSFET
and the allowable droop in gate drive voltage while the
high-side power MOSFET is conducting.
EQUATION 5-1:
Where:
CBOOT
≥
----Q-----G---A---T---E-----
ΔVDROOP
CBOOT = bootstrap capacitor value
QGATE = total gate charge of the high-
side MOSFET
ΔVDROOP = allowable gate drive voltage
droop
For example:
QGATE = 30 nC
ΔVDROOP = 200 mV
CBOOT ≥ 0.15 uF
A low ESR ceramic capacitor is recommend with a
maximum voltage rating that exceeds the maximum
input voltage, VCC, plus the maximum supply voltage,
VSUPPLY. It is also recommended that the capacitance
of CBOOT not exceed 1.2 uF.
5.2 Decoupling Capacitor
Proper decoupling of the MCP14628 is highly recom-
mended to help ensure reliable operation. This decou-
www.DataSheeptl4inUg.cocmapacitor should be placed as close to the
MCP14628 as possible. The large currents required to
quickly charge the capacitive loads are provided by this
capacitor. A low ESR ceramic capacitor is
recommended.
5.3 Power Dissipation
The power dissipated in the MCP14628 consists of the
power loss associated with the quiescent power and
the gate charge power.
The quiescent power loss can be calculated by the
following equation and is typically negligible compared
to the gate drive power loss.
MCP14628
EQUATION 5-2:
Where:
PQ = IVCC × VCC
PQ = Quiescent Power Loss
IVCC = No Load Bias Current
VCC = Bias Voltage
The main power loss occurs from the gate charge
power loss. This power loss can be defined in terms of
both the high-side and low-side power MOSFETs.
EQUATION 5-3:
PGATE = PHIGHDR + PLOWDR
PHIGHDR = VCC × QHIGH × FSW
PLOWDR = VCC × QLOW × FSW
Where:
PGATE = Total Gate Charge Power Loss
PHIGHDR = High-Side Gate Charge Power
Loss
PLOWDR = Low-Side Gate Charge Power
Loss
VCC = Bias Supply Voltage
QHIGH = High-Side MOSFET Total Gate
Charge
QLOW = Low-Side MOSFET Total GAte
Charge
FSW = Switching Frequency
5.4 PCB Layout
Proper PCB layout is important in a high current, fast
switching circuit to provide proper device operation.
Improper component placement may cause errant
switching, excessive voltage ringing, or circuit latch-up.
There are two important states of the MCP14628
outputs, high and low. Figure 5-1 depicts the current
flow paths when the outputs of the MCP14628 are high
and the power MOSFETs are turned on. Charge
needed to turn on the low-side power MOSFET comes
from the decoupling capacitor CVCC. Current flows from
this capacitor through the internal LOWDR circuitry,
into the gate of the low-side power MOSFET, out the
source, into the ground plane, and back to CVCC. To
reduce any excess voltage ringing or spiking, the
inductance and area of this current loop must be
minimized.
© 2008 Microchip Technology Inc.
DS22083A-page 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MCP14628.PDF ] | |
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