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PDF STHV748 Data sheet ( Hoja de datos )
| Número de pieza | STHV748 | |
| Descripción | 2A high-speed pulser | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STHV748
5-level, ±90 V, 2 A high-speed pulser
with four independent channels
Preliminary data
Features
■ High-density ultrasound transmitter
■ 0 to ±90 V output voltage
■ Up to 20 MHz operating frequency
■ Low-power, high-voltage drivers
■ 2 independently supplied half bridges for each
channel in pulse wave (PW) mode
– 5-level output waveform
– ±2 A source and sink current
– Down to 20 ps jitter
– Anti-cross conduction function
– Low 2nd harmonic distortion
– Fine-tuning on propagation delay
■ Fully integrated clamping-to-ground function
– 6 Ω synchronous active clamp
– Anti-leakage on output node
■ Dedicated half bridge for continuous wave
(CW) mode on each
– Down to 0.1 W power consumption
– ±0.6 A source and sink current
– Down to 10 ps jitter
www.DataS■heeFt4uUll.ycoimntegrated HV receiver switch
– 13.5 Ω on resistance
– HV MOS topology to minimize current
consumption
– Up to 300 MHz BW
■ 2.4 V to 3.6 V CMOS logic interface
■ Auxiliary integrated circuits
– Noise blocking diodes
– Fully self-biaising architecture
– Anti-memory effect for all internal HV
nodes
– Thermal protection
– Stand by function
■ Latch-up free due to HV SOI technology
■ Very few external passive components needed
QFN64 9 x 9 x1.0 mm
Applications
■ Medical ultrasound imaging
■ Pulse waveform generator
■ NDT ultrasound transmission
■ Piezoelectric transducers driver
Description
This monolithic, high-voltage, high-speed pulser
generator features four independent channels. It
is designed for medical ultrasound applications,
but can also be used for other piezoelectric,
capacitive or MEMS transducers. The device
comprises a controller logic interface circuit, level
translators, MOSFET gate drivers, noise blocking
diodes and high-power P-channel and N-channel
MOSFETs as output stage for each channel,
clamping-to-ground circuitry, anti-leakage, anti-
memory effect block, thermal sensor and HV
receiver switch (HVR_SW) which guarantees a
strong decoupling during transmission phase.
Moreover the STHV748 includes self biasing and
thermal shutdown blocks (see Figure 1).
Each channel can support up to five active output
levels with two half bridges. The output stage of
each channel is able to provide ±2 A peak output
current. In order to reduce power dissipation
during continuous wave mode, the peak current is
limited to 0.6 A (a dedicated half bridge is used).
Table 1. Device summary
Order code
Package
STHV748QTR
QFN64
Packaging
Tape and reel
January 2010
Doc ID 15450 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/22
www.st.com
22
1 page  
STHV748
Pin settings
Table 2. Pin description (P = power, A = analog, D = digital) (continued)
Pin N Name
Function
IN/OUT Type
12
HVOUT_B
Channel B, high-voltage output before noise blocking
diodes
13 HVM0_B Negative high-voltage supply 0 channel B
14 HVM1_B Negative high-voltage supply 1 channel B
15 REF_HVM0 Supply for low side 0 gate driver
16 D_CTR Delay control
17 IN4 Input signal shared
18 IN1_B Input signal channel B
19 IN2_B Input signal channel B
20 IN3_B Input signal channel B
21 VDDP Positive low-voltage supply
22 GND_PWR Power ground
23 XDCR_B Channel B, high-voltage output
24 LVOUT_B Channel B, low-voltage output
25 LVOUT_C Channel C, low-voltage output
OP
IP
IP
IP
IA
ID
ID
ID
ID
IA
IP
OP
OA
OA
26 XDCR_C Channel C, high-voltage output
27 GND_PWR Power ground
28 VDDM Negative low-voltage supply
29 IN3_C Input signal channel C
30 IN2_C Input signal channel C
31 IN1_C Input signal channel C
OP
IP
IA
ID
ID
ID
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32 THSD Thermal shutdown pin
33 AGND Signal ground
34 REF_HVM1 Supply for low side 1 gate driver
35 HVM1_C Negative high-voltage supply 1 channel C
36 HVM0_C Negative high-voltage supply 0 channel C
37
HVOUT_C
Channel C, high-voltage output before noise blocking
diodes
38 HVP0_C Positive high-voltage supply 0 channel C
39 REF_HVP1 Supply for high side 1 gate driver
40 HVP1_C Positive high-voltage supply 1 channel C
41 HVP1_D Positive high-voltage supply 1 channel D
42 REF_HVP0 Supply for high side 0 gate driver
I/O D
IA
IP
IP
IP
OP
IP
IP
IP
IP
IP
43 HVP0_D Positive high-voltage supply 0 channel D
44
HVOUT_D
Channel D, high-voltage output before noise blocking
diodes
IP
OP
Doc ID 15450 Rev 1
5/22
5 Page 
STHV748
Operating supply voltages and average currents
6.1
Digital inputs
Table 8. Digital inputs
Symbol
IN1_#, IN2_#, IN3_#, IN4, EN, THSD
IN1_#, IN2_#, IN3_#, IN4, EN, THSD
Parameter
Min.
Input logic high-voltage 0.8DVDD
Input logic low-voltage
0
Max. Units
DVDD
0.2DVDD
V
V
6.2
Output signals
Table 9. Output signals
Symbol
Parameter
HVOUT High-voltage output before noise blocking diodes
XDCR High-voltage output
LVOUT Low-voltage output
THSD Thermal shutdown pin
Min.
-90
-90
-1
0
Max.
90
90
1
3
Units
V
V
V
V
www.DataSheet4U.com
Doc ID 15450 Rev 1
11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet STHV748.PDF ] | |
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