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ADE7858 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADE7858
Beschreibung Polyphase Multifunction Energy Metering IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADE7858 Datasheet, Funktion
Data Sheet
Polyphase Multifunction Energy Metering IC
with Harmonic and Fundamental Information
ADE7854/ADE7858/ADE7868/ADE7878
FEATURES
Highly accurate; supports EN 50470-1, EN 50470-3,
IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards
Compatible with 3-phase, 3- or 4-wire (delta or wye), and
other 3-phase services
Supplies total (fundamental and harmonic) active, reactive
(ADE7878, ADE7868, and ADE7858 only), and apparent
energy, and fundamental active/reactive energy (ADE7878
only) on each phase and on the overall system
Less than 0.1% error in active and reactive energy over a
dynamic range of 1000 to 1 at TA = 25°C
Less than 0.2% error in active and reactive energy over a
dynamic range of 3000 to 1 at TA = 25°C
Supports current transformer and di/dt current sensors
Dedicated ADC channel for neutral current input (ADE7868 and
ADE7878 only)
Less than 0.1% error in voltage and current rms over a
dynamic range of 1000 to 1 at TA = 25°C
Supplies sampled waveform data on all three phases and on
neutral current
Selectable no load threshold levels for total and
fundamental active and reactive powers, as well as for
apparent powers
Low power battery mode monitors phase currents for
antitampering detection (ADE7868 and ADE7878 only)
Battery supply input for missing neutral operation
Phase angle measurements in both current and voltage
channels with a typical 0.3° error
Wide-supply voltage operation: 2.4 V to 3.7 V
Reference: 1.2 V (drift +5 ppm/°C typical) with external
overdrive capability
Single 3.3 V supply
40-lead lead frame chip scale package (LFCSP), Pb-free
Operating temperature: −40°C to +85°C
Flexible I2C, SPI, and HSDC serial interfaces
APPLICATIONS
Energy metering systems
GENERAL DESCRIPTION
The ADE7854/ADE7858/ADE7868/ADE7878 are high accuracy,
3-phase electrical energy measurement ICs with serial interfaces
and three flexible pulse outputs. The ADE78xx devices incorporate
second-order sigma-delta (Σ-∆) analog-to-digital converters
(ADCs), a digital integrator, reference circuitry, and all of the
signal processing required to perform total (fundamental and
harmonic) active, reactive (ADE7878, ADE7868, and
ADE7858), and apparent energy measurement and rms calcu-
lations, as well as fundamental-only active and reactive energy
measurement (ADE7878) and rms calculations. A fixed function
digital signal processor (DSP) executes this signal processing.
The DSP program is stored in the internal ROM memory.
The ADE7854/ADE7858/ADE7868/ADE7878 are suitable for
measuring active, reactive, and apparent energy in various 3-phase
configurations, such as wye or delta services, with both three
and four wires. The ADE78xx devices provide system calibration
features for each phase, that is, rms offset correction, phase
calibration, and gain calibration. The CF1, CF2, and CF3 logic
outputs provide a wide choice of power information: total active,
reactive, and apparent powers, or the sum of the current rms
values, and fundamental active and reactive powers.
The ADE7854/ADE7858/ADE7868/ADE7878 contain wave-
form sample registers that allow access to all ADC outputs. The
devices also incorporate power quality measurements, such as
short duration low or high voltage detections, short duration
high current variations, line voltage period measurement, and
angles between phase voltages and currents. Two serial interfaces,
SPI and I2C, can be used to communicate with the ADE78xx. A
dedicated high speed interface, the high speed data capture
(HSDC) port, can be used in conjunction with I2C to provide
access to the ADC outputs and real-time power information.
The ADE7854/ADE7858/ADE7868/ADE7878 also have two
interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled
interrupt event has occurred. For the ADE7868/ADE7878, three
specially designed low power modes ensure the continuity of
energy accumulation when the ADE7868/ADE7878 is in a tam-
pering situation. See Table 1 for a quick reference chart listing
each part and its functions. The ADE78xx are available in the
40-lead LFCSP, Pb-free package.
Table 1. Part Comparison
Part No.
IRMS,
VRMS,
and
WATT VAR VA
ADE7878 Yes
Yes Yes
ADE7868 Yes
Yes Yes
ADE7858 Yes
Yes Yes
ADE7854 Yes
No Yes
di/dt
Yes
Yes
Yes
Yes
Fundamental
WATT and
VAR
Yes
No
No
No
Tamper
Detect and
Low Power
Modes
Yes
Yes
No
No
Rev. H
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADE7858 Datasheet, Funktion
ADE7854/ADE7858/ADE7868/ADE7878
Data Sheet
Figure 2. ADE7858 Functional Block Diagram
Rev. H | Page 6 of 100

6 Page









ADE7858 pdf, datenblatt
ADE7854/ADE7858/ADE7868/ADE7878
Data Sheet
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams; see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions.
Table 3. I2C-Compatible Interface Timing Parameter
Parameter
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of SCL Clock
High Period of SCL Clock
Set-Up Time for Repeated Start Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Suppressed Spikes
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
tSP
Standard Mode
Min Max
0 100
4.0
4.7
4.0
4.7
0 3.45
250
1000
300
4.0
4.7
N/A1
Fast Mode
Min Max
0 400
0.6
1.3
0.6
0.6
0 0.9
100
20 300
20 300
0.6
1.3
50
Unit
kHz
μs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
1 N/A means not applicable.
SDA
tF
tLOW
tR
SCLK
tHD;STA tHD;DAT
START
CONDITION
tSU;DAT
tF
tHD;STA
tHIGH
tSU;STA
REPEATED START
CONDITION
Figure 5. I2C-Compatible Interface Timing
tSP tR
tBUF
tSU;STO
STOP
START
CONDITION CONDITION
Rev. H | Page 12 of 100

12 Page





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