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WCMB4016R4X Schematic ( PDF Datasheet ) - Weida Semiconductor

Teilenummer WCMB4016R4X
Beschreibung 256K x 16 Static RAM
Hersteller Weida Semiconductor
Logo Weida Semiconductor Logo 




Gesamt 12 Seiten
WCMB4016R4X Datasheet, Funktion
WCMB4016R4X
Features
• Low voltage range:
1.65V1.95V
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 2 mA @ f = fmax (70 ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMB4016R4X is a high-performance CMOS static
RAM organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This device is ideal for portable applications such as cellular
telephones. The device also has an automatic power-down
feature that significantly reduces power consumption by 99%
when addresses are not toggling. The device can also be put
into standby mode when deselected (CE HIGH or both BLE
Logic Block Diagram
www.DataSheet4U.com
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K x 16
RAM Array
2048 X 2048
256K x 16 Static RAM
and BHE are HIGH). The input/output pins (I/O0 through I/O15)
are placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The WCMB4016R4X is available in a 48-ball FBGA package.
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Created January 17, 2002






WCMB4016R4X Datasheet, Funktion
Switching Waveforms
[12, 13]
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
WCMB4016R4X
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
OE
BHE/BLE
DATA OUT
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VCC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tRC
Notes:
12. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL..
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW.
DATA VALID
tPD
tHZCE
tHZOE
tHZBE
HIGH
IMPEDANCE
50%
ICC
ISB
Page 6 of 12

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WCMB4016R4X pdf, datenblatt
WCMB4016R4X
Document Title: WCMB4016R4X, 256K x 16 Static RAM
REV.
Spec #
ECN #
Issue Date
** 38-14012
115228
1/17/02
Orig. of Change Description of Change
MGN
New Data Sheet
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