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PDF ML67Q5002 Data sheet ( Hoja de datos )
| Número de pieza | ML67Q5002 | |
| Descripción | (ML675001 - ML675003) 32-bit ARM-Based General-Purpose Microcontroller | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML67Q5002 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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OKI Semiconductor
ML675001/Q5002/Q5003
32-bit ARM-Based General-Purpose Microcontroller
FEDL675001-01
Issue Date: Dec. 15, 2003
GENERAL DESCRIPTION
The ML675001, ML67Q5002, and ML67Q5003 microcontrollers (MCUs) are the members of an extensive and
growing family of 32-bit ARM®-based standard products for general-purpose applications that require 32-bit
CPU performance and low cost afforded by MCU integrated features.
ML675001/67Q5002/67Q5003 provide 8KB unified cache memory, built-in 32Kbyte SRAM, built-in 4Kbyte
boot ROM, and a host of other useful peripherals such as auto-reload timers, watchdog timer (WDT),
pulse-width modulators (PWM), A-to-D converter, expanded UARTs, synchronous serial port, I2C serial
interface, GPIOs, DMA controller, external memory controller, and boundary scan capability. In addition, the
ML67Q5002 and ML67Q5003 offer 256 Kbytes and 512 Kbytes of built-in Flash memory respectively. The
ML675001, ML67Q5002 and ML67Q5003 are pin-to-pin compatible with each other, and are pin-to-pin
compatible with ML674001 Series for easy performance updates.
Oki’s ML675K Family MCUs are capable of executing both the 32-bit ARM instruction set for
high-performance applications as well as the 16-bit Thumb® instruction set for high code-density,
power-efficient applications. With an ARM7TDMI® core operating at 60 MHz maximum frequency, ARM
Thumb™ capabilities, and robust feature sets, the ML675001 Series MCUs are suitable for an array of
applications including high performance industrial controllers and instrumentation, telecom, PC peripherals,
security/surveillance, test equipment, and a variety of consumer electronics devices.
The ARM7TDMI® Advantage
Oki’s ML675K Family of low-cost ARM-based MCUs offers system designers a bridge from 8- and 16-bit
proprietary MCU architectures to ARM’s higher-performance, affordable, widely-accepted industry standard
architecture and its industry-wide support infrastructure. The ARM industry infrastructure offers the system
developers many advantages including software compatibility, many ready-to-use software applications, large
choices among hardware and software development tools. These ARM-based advantages allow Oki’s
customers to better leverage engineering resources, lower development costs, minimize project risks, and reduce
their product time to market. In addition, migration of a design with an Oki standard MCU to an Oki custom
www.DataShsoeelut4tiUo.ncoims easily facilitated with its award-winning uPLAT™ product development architecture.
FEATURES
•CPU
32-bit RISC CPU (ARM7TDMI)
32-bit instructions (ARM Instructions) and 16-bit instructions (Thumb Instructions) mixed
General purpose registers : 31 x 32 bits
Built-in Barrel shifter and multiplier (32 bit x 8 bit, Modified Booth’s Algorithm)
Little endian
Built-in debug function
Cache memory
8KB unified memory
4 way set-associative
•Internal memory
RAM 32KB (32-bit access)
FLASH (16-bit access)
ML675001
: ROM-less version
ML67Q5002
: 256Kbytes
ML67Q5003
: 512Kbytes
ARM, ARM7TDMI, Multi-ICE and AMBA are registered trademarks of ARM Ltd., UK.
µPLAT is Oki's trademark.
The contents of this data sheet are subject to change for modification without notice.
1/24
1 page  
OKI Semiconductor
144-Pin Plastic LQFP
FEDL675001-01
ML675001/67Q5002/67Q5003
(Secondary fun(Primary function)
SIN
SOUT
CTS
DSR
DCD
DTR
RTS
www.DataSheet4RUI .com
SDA
SCL
STXD
PLLVDD
PLLGND
CKO
JSEL
TMS
TCK
DRAME_N
CKOE_N
GND
OSC0
OSC1_N
VDD_IO
TEST
PIOA[0]
PIOA[1]
AVDD
VREFP
AIN[0]
AIN[1]
AIN[2]
AIN[3]
VREFN
AGND
GND
PIOA[2]
VDD_IO
PIOA[3]
PIOA[4]
VDD_CORE
PIOA[5]
PIOA[6]
PIOA[7]
GND
PIOE[3]
PIOE[4]
PIOB[6]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
144pin LQFP
(TOP VIEW)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
(Primary functi (Secondary f
XIOCS_N[3]
XIOCS_N[2]
XIOCS_N[1]
GND
XIOCS_N[0]
XRAMCS_N
XROMCS_N
XBWE_N[1]
XBWE_N[0]
XWE_N
VDD_IO
XOE_N
PIOC[7]
PIOC[6]
VDD_CORE
PIOC[5]
PIOC[4]
PIOC[3]
VDD_IO
PIOC[2]
XA[18]
GND
XA[17]
XA[16]
XA[15]
GND
XA[14]
XA[13]
XA[12]
XA[11]
XA[10]
VDD_IO
XA[9]
XA[8]
XA[7]
XA[6]
XWR
XA[23]
XA[22]
XA[21]
XA[20]
XA[19]
Notes: NC pins are electrically unconnected in the package.
NC pins can be connected to Vdd or GND.
5/24
5 Page 
OKI Semiconductor
FEDL675001-01
ML675001/67Q5002/67Q5003
Pin Name
I/O
Description
External Bus
XA[23:19]
O Address bus to external RAM, external ROM, external I/O banks, and
external DRAM. After a reset, these pins are configured for their primary
function (PIOC[6:2]).
XA[18:0]
O Address bus to external RAM, external ROM, external I/O banks, and
external DRAM.
XD[15:0]
I/O Data bus to external RAM, external ROM, external I/O banks, and external
DRAM.
External bus control signals (ROM/SRAM/IO)
XROMCS_N
O ROM bank chip select
XRAMCS_N
XIOCS_N[0]
O SRAM bank chip select
O IO chip select 0
XIOCS_N[1]
O IO chip select 1
XIOCS_N[2]
XIOCS_N[3]
O IO chip select 2
O IO chip select 3
XOE_N
O Output enable/ Read enable
XWE_N
XBS_N[1:0]
O Write enable
O Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB
XBWE_N[0]
XBWE_N[1]
O LSB Write enable
O MSB Write enable
XWR
O Data transfer direction for external bus, used when connecting to Motorola
I/O devices. This represent the secondary function of pin PIOC[7].
L: read , H: write. Available for I/O bank 0/1.
XWAIT
I External I/O bank 0/1/2/3 WAIT signal.
www.DataSheet4U.com
This input permits access to devices slower than register settings.
External bus control signals (DRAM)
XRAS_N
O Row address strobe. Used for both EDO DRAM and SDRAM
XCAS_N
XSDCLK
O Column address strobe signal (SDRAM)
O SDRAM clock (same frequency as internal HCLK)
XSDCKE
O Clock enable (SDRAM)
XSDCS_N
XDQM[1]/XCAS_N[1]
XDQM[0]/XCAS_N[0]
O Chip select (SDRAM)
O Connected to SDRAM: DQM (MSB)
Connected to EDO DRAM: column address strobe signal (MSB)
O Connected to SDRAM: DQM (LSB)
Connected to EDO DRAM: column address strobe signal (LSB)
Primary /
Secondary
Secondary
—
—
—
—
—
—
—
—
—
—
—
—
—
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Logic
Positive
Positive
Positive
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
—
Positive
Negative
Negative
—
—
Negative
Positive/
Negative
Positive/
Negative
11/24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ML67Q5002.PDF ] | |
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