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PDF ML670100 Data sheet ( Hoja de datos )
| Número de pieza | ML670100 | |
| Descripción | High-Performance CMOS 32-Bit Single Chip Microcontroller | |
| Fabricantes | OKI electronic | |
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Semiconductor
ML670100
Version 2
Aug., 1999
OKI’s High-Performance CMOS 32-Bit Single Chip Microcontroller
GENERAL DESCRIPTION
The ML670100 is a high-performance 32-bit microcontroller combining a RISC based, 32-bit CPU core -
the ARM7TDMITM - with memory and such peripheral circuits as timers, serial ports, and analog-to-
digital converter. This combination of 32-bit data processing, built-in memory, and on-chip peripherals
make it ideal for controlling equipment requiring both high speed and high functionality. An external
memory controller supports direct connection to memory and peripheral devices for adding even more
functionality.
FEATURES
Operating Voltage 2.7 to 3.6V
Operating Frequency 25MHz maximum(3.0 to 3.6V)
On-chip memory -ROM: 128 kilobytes
-RAM: 4 kilobytes
I/O Function
I/O ports: 8 bits x 9, I/O directions are specified at the bit level
Timer
-Flexible timer (16-bit multi-function timer with six channels)
Choice of operating modes: auto-reload timer, compare output, PWM
and capture
-Time base counter with WDT function
Serial Port
-One asynchronous serial port (UART) with baud rate generator
-Two clock synchronous serial port
A-to-D Converter -8-bit resolution A-to-D converter with eight analog input ports
Interrupt
-Support for 28 interrupt sources: 9 external and 19 internal
Controller
-Choice of eight priority levels for each source
www.DataSheet4U.coEmxternal Memory -Direct connection to ROM, SRAM, DRAM and peripheral devices
Controller
-Support for four banks: two for ROM, SRAM and I/O devices plus two for
DRAM
-User-configurable bus width (8/16 bits) and wait control and other
parameters for accessing memory and external devices
Clock Generator -Built-in crystal oscillation circuit and PLL
-Choice of divider ratio (1/1, 1/2, 1/4) for adjusting operating clock frequency
to match the load of processing
Package
144-pin LQFP ( LQFP144-P-2020-0.50-K)
ARM POWERED logo is the registered trademark of ARM Limited. ARM7TDMI is the trademark of ARM Limited.
The Information contained herein can change without notice owing to product and/or technical improvement.
The signal name of negative logic is being changed to nXXX from XXX in this data sheet.
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Semiconductor
PIN DESCRIPTIONS (Cont.)
ML670100
Type Signal Name I/O Direction Description
Bus nBREQ
Input
This input is a bus request signal from an external device.
control
It represents a secondary function for I/O port PIO7[6].
signals nBACK
Output
This output is an acknowledgment signal to a bus request signal
from an external device. It represents a secondary function for
I/O port PIO7[7].
Interru- nEFIQ
Input
This input is an external fast interrupt request (FIQ). When
pts accepted, the request is processed as an FIQ exception.
nEIR[7:0] Input
This inputs are external interrupt requests. They represent
secondary functions for I/O port PIO3[7:0].
Timers TMIN[5:0] Input
These pins function as capture trigger input pins for Flexible
Timer channels 5-0 in capture mode. They represent secondary
functions for I/O port PIO4[5:0].
TMOUT[5:0] Output
These pins function as output pins for Flexible Timer channels
5-0 in compare output or PWM mode. They represent
secondary functions for I/O port PIO4[5:0].
TMCLK[1:0] Input
These pins function as Flexible Timer channels 1 and 0 clock
input pins. They represent secondary functions for I/O port
PIO4[7:6].
Serial ASI_TXD Output
This output is the transmit data for the Asynchronous Serial
ports
Interface. It represents a secondary function for I/O port
PIO5[7].
ASI_RXD Input
This input is the receive data for the Asynchronous Serial
Interface. It represents a secondary function for I/O port
PIO5[6].
CSI0_TXD Output
This output is the transmit data for the Clock Synchronous
Serial Interface 0. It represents a secondary function for I/O
port PIO5[2].
CSI0_RXD Input
This input is the receive data for the Clock Synchronous Serial
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Interface 0. It represents a secondary function for I/O port
PIO5[1].
CSI0_SCLK Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 0. It represents a secondary
function for I/O port PIO5[0].
CSI1_TXD Output
This output is the transmit data for the Clock Synchronous
Serial Interface 1. It represents a secondary function for I/O
port PIO5[5].
CSI1_RXD Input
This input is the receive data for the Clock Synchronous Serial
Interface 1. It represents a secondary function for I/O port
PIO5[4].
CSI1_SCLK Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 1. It represents a secondary
function for I/O port PIO5[3].
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Semiconductor
CONFIGURATIONS of PINS and I/O PORTS
Input Pins (nRST, nEA, DBSEL, TEST, nEFIQ, FSEL, PLLEN, VCOM)
VDD
ML670100
Input pins
(high impedance)
Output Pin (CLKOUT)
GND
VDD
GND
Output pin
(CMOS output)
Tri-state output pins (XA23 - XA1, nLB/XA0, nCS0, nRD, nWRE/nWRL)
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Output enable
signal
Output pins
(CMOS output when enabled)
Bidirectional pins (XD7 - XD0)
Output enable
signal
Bidirectional pins
(CMOS output when enabled)
Read signal
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