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CG6264AM Schematic ( PDF Datasheet ) - Weida Semiconductor

Teilenummer CG6264AM
Beschreibung 2Mb (128K x 16) Pseudo Static RAM
Hersteller Weida Semiconductor
Logo Weida Semiconductor Logo 




Gesamt 12 Seiten
CG6264AM Datasheet, Funktion
ADVANCE INFORMATION
CG6264AM
2Mb (128K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access Time: 70ns
• Ultra-low active power
— Typical active current: 2.0mA @ f = 1 MHz
— Typical active current: 13mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, CE2, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48 Ball BGA Package
Functional Description[1]
The CG6264AM is a high-performance CMOS Pseudo static
RAM organized as 128K words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life® (MoBL) in
portable applications such as cellular telephones. The device
can be put into standby mode reducing power consumption by
more than 99% The device can also be put into standby mode
when deselected (CE HIGH or CE2 LOW or both BHE and BLE
are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CEHIGH
or CE2 LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, CE2 HIGH and WE
LOW). The addresses must not be toggled once the read
is started on the device.
Writing to the device is accomplished by taking Chip Enables
(CE LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A17). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enables (CE LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this
datasheet for a complete description of read and write modes
Logic Block Diagram
www.DataSheet4U.com
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K × 16
RAM Array
COLUMN DECODER
I/O0 – I/O7
I/O8 – I/O15
BHE
WE
OE
CE2
CE
BLE
Power- Down
Circuit
BHE
BLE
CE2
CE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Weida Semiconductor, Inc.
38-XXXXX
Revised Feb 2004






CG6264AM Datasheet, Funktion
ADVANCE INFORMATION
CG6264AM
Switching Characteristics Over the Operating Range[11]
70 ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
tLZBE
tHZBE
tSK
WRITE CYCLE[13]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[12, 14]
OE HIGH to High Z[12, 14]
CE LOW and CE2 HIGH to Low Z[12, 14]
CE HIGH and CE2 LOW to High Z[12, 14]
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[12, 14]
BLE / BHE HIGH to HIGH Z[12, 14]
Address Skew
70 ns
70 ns
10 ns
70 ns
35 ns
5 ns
25 ns
5 ns
25 ns
70 ns
5 ns
25 ns
0 ns
tWC Write Cycle Time
70 ns
tSCE CE LOW and CE2 HIGH to Write End
60
ns
tAW Address Set-Up to Write End
60
ns
tHA Address Hold from Write End
0
ns
tSA Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
45 ns
tBW BLE / BHE LOW to Write End
60
ns
www.DattaSSDheet4U.com
tHD
tHZWE
tLZWE
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z[12, 14]
WE HIGH to Low-Z[12, 14]
45 ns
0 ns
25 ns
5 ns
Notes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section..
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the
signal that terminates the write.
14. High-Z and Low-Z parameters are characterized and are not 100% tested.
38-XXXXX
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CG6264AM pdf, datenblatt
ADVANCE INFORMATION
Document Title: CG6264AM MoBL3® 2Mb (128K x 16) Pseudo Static RAM
Document Number: 38-XXXXX
REV.
ECN NO.
Issue
Date
Orig. of
Change Description of Change
** 10/16/03 MPR New Datasheet
CG6264AM
www.DataSheet4U.com
38-XXXXX
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