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D72852 Schematic ( PDF Datasheet ) - NEC

Teilenummer D72852
Beschreibung UPD72852
Hersteller NEC
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Gesamt 30 Seiten
D72852 Datasheet, Funktion
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72852
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
The µPD72852 is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
The µPD72852 supports transfers of up to 400 Mbps and consumes less power than the µPD72850B. The
µPD72852 is suitable for battery systems with an IEEE1394 interface.
FEATURES
• The two-port physical layer LSI complies with IEEE1394a-2000
• Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)
• Meets IntelTM Mobile Power Guideline 2000
• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-
speed concatenation, arbitration acceleration, fly-by concatenation
• Fully compliant with OHCI requirements
• Small package: 64-pin plastic LQFP
• Super low power: 68 mA (Operating mode)
: 115 µA (Suspend mode)
• Data rate: 400/200/100 Mbps
• Supports PHY pinging and remote PHY access packets
• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)
• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
• 64-bit flexible register incorporated in PHY register
www.DataSheet4UE.cloemctrically isolated Link interface
• Supports LPS/Link-on as part of PHY/Link interface
• External filter capacitors for PLL not required
• Extended Resume signaling for compatibility with legacy DV devices
• System power management by signaling of node power class information
• Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number
µPD72852GB-8EU
Package
64-pin plastic LQFP (10 x 10)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14920EJ3V0DS00 (3rd edition)
Date Published March 2001 NS CP(K)
Printed in Japan
The mark shows major revised points.
2000






D72852 Datasheet, Funktion
µPD72852
4.4 Acceleration Control ..................................................................................................................... 27
4.5 Transmit Status ............................................................................................................................. 28
4.6 Transmit ......................................................................................................................................... 29
4.7 Cancel............................................................................................................................................. 30
4.8 Receive ........................................................................................................................................... 31
5. CABLE PHY PACKET ........................................................................................................................... 32
5.1 Self_ID Packet ................................................................................................................................ 32
5.2 Link-on Packet ............................................................................................................................... 33
5.3 PHY Configuration Packet ............................................................................................................ 33
5.4 Extended PHY Packet ................................................................................................................... 33
5.4.1 Ping Packet........................................................................................................................................... 34
5.4.2 Remote Access Packet......................................................................................................................... 34
5.4.3 Remote Reply Packet ........................................................................................................................... 35
5.4.4 Remote Command Packet .................................................................................................................... 35
5.4.5 Remote Confirmation Packet ................................................................................................................ 36
5.4.6 Resume Packet..................................................................................................................................... 36
6. ELECTRICAL SPECIFICATIONS.......................................................................................................... 37
7. APPLICATION CIRCUIT EXAMPLE ..................................................................................................... 42
8. PACKAGE DRAWING ........................................................................................................................... 43
9. RECOMMENDED SOLDERING CONDITIONS................................................................................... 44
www.DataSheet4U.com
6 Data Sheet S14920EJ3V0DS

6 Page









D72852 pdf, datenblatt
µPD72852
2.2 Port Status Page (Page 000)
1000
1001
1010
1011
1100
1101
1110
1111
Figure 2-2. Port Status Page
01
AStat
Negotiated_speed
234
BStat
Child
Int_enable
Fault
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
Connected
6
Bias
Reserved
7
Disabled
Field
AStat
BStat
Child
Connected
Bias
www.DataSheet4U.com
Disabled
Negotiated_
speed
Int_enable
Fault
Reserved
Table 2-2. Bit Field Description
Size
2
2
1
1
1
1
3
1
1
-
R/W
R
R
R
R
R
R/W
R
R/W
R/W
R
Reset value
XX
XX
0
See
Description
0
0
000…
Description
A port status value.
00: invalid, 10: “0”
01: “1”, 11: “Z”
B port status value.
00: invalid, 10: “0”
01: “1”, 11: “Z”
Child node status value.
1: Connected to child node
0: Connected to parent node
Connection status value.
1: Connected
0: Disconnected
Bias voltage status value.
1: Bias voltage
0: No bias voltage
The reset value is set to 0: Enabled.
Shows the maximum data transfer rate of the node connected to this port.
000: 100 Mbps
001: 200 Mbps
010: 400 Mbps
When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias,
Disabled or Fault bits change state.
This bit has no effect when SUS/RES(19pin) = “0”.
Set to 1 if an error occurs during Suspend/Resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
This bit has no effect when SUS/RES(19pin) = “0”
Reserved. Read as 0.
12 Data Sheet S14920EJ3V0DS

12 Page





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