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PDF SMB214C Data sheet ( Hoja de datos )

Número de pieza SMB214C
Descripción Three-channel Programmable DC-DC System Power Managers
Fabricantes Summit Microelectronics 
Logotipo Summit Microelectronics Logotipo



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No Preview Available ! SMB214C Hoja de datos, Descripción, Manual

SMB214A/B/C
Preliminary Information
High-power, Three-channel Programmable DC-DC System Power Managers
FEATURES & APPLICATIONS
INTRODUCTION
Digital programming of all major parameters via
I2C interface and non-volatile memory
Output voltage set point
Input/battery voltage monitoring
Output power-up/down sequencing
Dynamic voltage control of all outputs
UV/OV monitoring of all outputs
Enable/Disable outputs independently
User friendly Graphical User Interface (GUI)
Three synchronous step-down output channels
Integrated RESET monitor
+2.7V to +6.0V Input Range
Highly accurate output voltage: <2.5%
Factory programmable dead times
0% to 100% Duty Cycle operation
Undervoltage Lockout (UVLO) with hysteresis
Operating frequency: 400kHz (SMB214A), 800kHz
(SMB214B), 1MHz (SMB214C)
Applications
Car & Marine Navigation Systems
Set-top Boxes
TVs
DDR Memory
Mobile Computing/PDAs
Office Equipment
DMB Systems
www.DataSheet4U.com
SIMPLIFIED APPLICATIONS DRAWING
The SMB214A/B/C are highly integrated and flexible three-
channel power managers designed for use in a wide range of
applications. The built-in digital programmability allows system
designers to custom tailor the device to suit almost any multi-
channel power supply application from digital camcorders to
set-top boxes. Complete with a user friendly GUI, all
programmable settings, including output voltages and
input/output voltage monitoring, can be customized with ease.
The SMB214A/B/C integrate all the essential blocks required to
implement a complete three-channel power subsystem
consisting of three synchronous step-down “buck” controllers.
Additionally sophisticated power control/monitoring functions
required by complex systems are built-in. These include
digitally programmable output voltage set point, power-
up/down sequencing, enable/disable, dynamic voltage
management and UV/OV monitoring on all channels.
The integration of features and built-in flexibility of the
SMB214A/B/C allows the system designer to create a “platform
solution” that can be easily modified via software without major
hardware changes. Combined with the re-programmability of
the SMB214A/B/C, this facilitates rapid design cycles and
proliferation from a base design to future product generations.
The SMB214A/B/C are suited to a wide variety of applications
with an input range of +2.7V to +6.0V. Higher input voltage
operation can easily be implemented with a small number of
external components. Output voltages are extremely accurate
(<2.5%). Communication is accomplished via the industry
standard I2C bus. All user-programmed settings are stored in
non-volatile EEPROM. The devices are offered in both the
commercial and the industrial operating temperature range.
The package type is a lead-free, RoHS compliant, 5x5 QFN-
32.
+2.7V to +6.0V
or
Li-Ion
SMB214
I2C/SMBus
Enable Input
RESET Output
(Power Good)
System
Control
and
Monitoring
RESET
Monitor
3 Step-
Down
(Buck)
Channels
+0.5V to Vin (Prog.) @ 5A
CPU Core
+0.5V to Vin (Prog.) @ 5A
Memory, I/O
+0.5V to Vin (Prog.) @ 5A
Analog/RF
Figure 1 – Applications schematic featuring the SMB214A/B/C programmable DC-DC controllers.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT Microelectronics, Inc. 2007
757 N. Mary Avenue • Sunnyvale CA 94085
http://www.summitmicro.com/
2128 2.0 6/20/2008
Phone 408 523-1000 • FAX 408 523-1266
1

1 page




SMB214C pdf
SMB214A/B/C
PIN DESCRIPTION
Pin Number Pin Type
1 OUT
2 OUT
3 IN
4 IN
5 IN
6
7
www.DataShe8et4U.com
9
I/O
IN
OUT
PWR
10 OUT
11 IN
12 IN
13 IN
Summit Microelectronics, Inc
Pin Name
HSDRV_CH0
HEALTHY
(nRESET)
COMP1_CH0
COMP2_CH0
VM_CH0
SDA
SCL
LSDRV_CH1
HVSUP1
HSDRV_CH1
HOST_RESET
COMP1_CH1
COMP2_CH1
Pin Description
The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper
switching node of the channel 0 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH0 and assertion of
LSDRV_CH0 to prevent excessive current flow during switching.
The HEALTHY pin is an open drain output. High when all
enabled output supplies are within the programmed levels.
HEALTHY will ignore any disabled supply. There is a
programmable glitch filter on the under-voltage and over-voltage
sensors so that short transients outside of the limits will be
ignored by HEALTHY. This pin can also be programmed to act
as a Reset Output (nRESET). In this case, it releases with a
programmable delay after all outputs are valid. When used, this
pin should be pulled high by an external pull-up resistor.
The COMP1_CH0 (Channel 0 primary Compensation) pin is the
primary feedback input of the channel 0 step-down buck
controller. The COMP1_CH0 pin is internally connected to a
programmable resistor divider.
The COMP2_CH0 (Channel 0 secondary Compensation) pin is
the secondary feedback input of the channel 0 step-down buck
controller.
The VM_CH0 (Channel 0 Voltage Monitor) pin connects the
channel 0 step-down controller output. Internally the VM_CH0 pin
connects to a programmable resistor divider.
SDA (Serial Data) is an open drain bi-directional pin used as the
I2C data line. SDA must be tied high through a pull-up resistor.
SCL (Serial Clock) is an open drain input pin used as the I2C
clock line. SCL must be tied high through a pull-up resistor.
The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of n-channel MOSFET.
Channel 1 High Voltage Supply for Channel 1 buck driver.
The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH1 and assertion of
LSDRV_CH1 to prevent excessive current flow during switching.
The HOST_RESET pin is an active high reset input. When this
pin is asserted high, the nRESET output will immediately go low.
When HOST_RESET is brought low, nRESET will go high after a
programmed reset delay. When pin 2 is used as a HEALTHY
output, this pin needs to be attached to GND or VBATT via a
resistor.
The COMP1_CH1 (Channel 1 primary Compensation) pin is the
primary compensation input of the channel 1 step-down buck
controller. The COMP1_CH1 pin is internally connected to a
programmable resistor divider.
The COMP2_CH1 (Channel 1 secondary Compensation) pin is
the secondary compensation input of the channel 1 step-down
buck controller.
2128 2.0 6/20/2008
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SMB214C arduino
SMB214A/B/C
AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Note 4
Symbol Description
Conditions
Min Typ Max Unit
1.5
tPPTO
Programmable power-On Programmable power-on sequence
sequence timeout period. position to sequence position delay.
12.5
25
ms
50
1.5
tDPOFF
Programmable power-off Programmable power-off sequence
sequence timeout period. position to sequence position delay.
12.5
25
ms
Time between active enable in which
tPST
Programmable sequence
termination period
corresponding outputs must exceed there
programmed under voltage threshold. If
exceeded, a force shutdown will be
initiated.
50
OFF
50
100
200
ms
tPGF
Programmable glitch filter
Period for which fault must persist before
fault triggered actions are taken.
0
8 µs
Applicable when HEALTHY pin is used as
25
tRESET
Reset timeout period
an nRESET output pin. Programmable
time following assertion of last supply
50
100 ms
before nRESET pin is released high.
200
400
200
100
www.DSaRtaRSEhFeet4U.comPrerfoegreranmcemable slew rate
Adjustable slew rate factor proportional to
output slew rate.
67
50
V/s
33
25
20
Channels 0 to 2
tRL LS Driver output rise time CG=100pF, VBATT=4.2V
4.2 ns
tFL LS Driver output fall time CG=100pF, VBATT=4.2V
4.2 ns
tRL HS Driver output rise time CG=100pF, VBATT=4.2V
2.9 ns
tFL HS Driver output fall time CG=100pF, VBATT=4.2V
2.9 ns
High to low transition on HSDRV
tDT
Driver non-overlap delay
Low to high transition on buck HSDRV
30
ns
60
Note 4: Timing specifications are 20% shorter for the SMB214C device and 60% longer for SMB214A.
Summit Microelectronics, Inc
2128 2.0 6/20/2008
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