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PDF CY14B256LA Data sheet ( Hoja de datos )
| Número de pieza | CY14B256LA | |
| Descripción | 256 Kbit (32K x 8) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY14B256LA
256 Kbit (32K x 8) nvSRAM
Features
■ 25 ns and 45 ns Access Times
■ Internally Organized as 32K x 8 (CY14B256LA)
■ Hands off Automatic STORE on Power Down with only a Small
Capacitor
■ STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
■ RECALL to SRAM Initiated by Software or Power Up
■ Infinite Read, Write, and Recall Cycles
■ 1 Million STORE Cycles to QuantumTrap
■ 20 year Data Retention
■ Single 3V +20% to -10% Operation
■ Industrial Temperature
■ 44-Pin TSOP - II, 48-Pin SSOP, and 32-Pin SOIC Packages
■ Pb-free and RoHS Compliance
Functional Description
The Cypress CY14B256LA is a fast static RAM, with a nonvol-
atile element in each memory cell. The memory is organized as
32K bytes of 8 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
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Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54707 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 08, 2009
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CY14B256LA
Device Operation
The CY14B256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the Truth Table For SRAM Operations on page 16 for a
complete description of read and write modes.
SRAM Read
The CY14B256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0-14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
is initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
wwwK.DeaetpaSOheEetH4UIG.cHomduring the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14B256LA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 7. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull up on WE to hold it inactive during power up. This pull up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power up. This must be verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
VCC
0.1uF
VCC
WE VCAP
VSS
VCAP
Hardware STORE Operation
The CY14B256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256LA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
Document Number: 001-54707 Rev. *B
Page 5
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CY14B256LA
AC Switching Characteristics
Parameters
Cypress
Parameters
Alt
Parameters
SRAM Read Cycle
tACE
tACS
tRC[11]
tRC
tAA[12]
tAA
tDOE
tOE
tOHA[12]
tOH
tLZCE[10, 13]
tLZ
tHZCE[10, 13]
tHZ
tLZOE[10, 13]
tOLZ
tHZOE[10, 13]
tOHZ
tPU[10]
tPA
tPD[10]
tPS
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE[10, 13,14]
tLZWE[10, 13]
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
25 ns
Min Max
25
25
25
12
3
3
10
0
10
0
25
25
20
20
10
0
20
0
0
10
3
Switching Waveforms
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Figure 5. SRAM Read Cycle #1: Address Controlled [11, 12, 15]
45 ns
Min Max
45
45
45
20
3
3
15
0
15
0
45
45
30
30
15
0
30
0
0
15
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address
Data Output
Previous Data Valid
tOHA
tRC
Address Valid
tAA
Output Data Valid
Notes
11. WE must be HIGH during SRAM read cycles.
12. Device is continuously selected with CE and OE LOW.
13. Measured ±200 mV from steady state output voltage.
14. If WE is low when CE goes low, the outputs remain in the high impedance state.
15. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-54707 Rev. *B
Page 11
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| PDF Descargar | [ Datasheet CY14B256LA.PDF ] | |
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