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28F128L18 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 28F128L18
Beschreibung (28FxxxL18) StrataFlash Wireless Memory
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
28F128L18 Datasheet, Funktion
www.DataSheet4U.com
Intel StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
High performance Read-While-Write/Erase
— 85 ns initial access
— 54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 1.8 V low-power buffered programming at
7 µs/byte (Typ)
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
— Multiple 16-Mbit partitions: 256-Mbit devices
— Four 16-Kword parameter blocks: top or
bottom configurations
— 64-Kword main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status Register for partition and device status
Power
— VCC (core) = 1.7 V - 2.0 V
— VCCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby current: 30 µA (Typ) for 256-Mbit
— 4-Word synchronous read current: 15 mA (Typ)
at 54 MHz
— Automatic Power Savings mode
Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
Density and Packaging
— 64-, 128-, and 256-Mbit density in VF BGA
packages
— 128/0 and 256/0 density in SCSP
— 16-bit wide data bus
The Intel StrataFlash® wireless memory (L18) device is the latest generation of Intel
StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-
standard chip scale packaging.
Order Number: 251902, Revision: 009
April 2005






28F128L18 Datasheet, Funktion
Intel StrataFlash® Wireless Memory (L18)
Revision History
Revision Date Revision
Description
10/15/02
01/20/03
04/11/03
08/04/03
01/20/04
05/22/04
www.DataSheet4U.com
-001
-002
-003
-004
-005
-006
Initial Release
Revised 256-Mbit Partition Size
Revised 256-Mbit Memory Map
Change WAIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all
Writes)
Change WAIT function to active during Synchronous Non-Array Read
Updated all Waveforms to reflect new WAIT function
Revised Section 8.2.2
Added Synchronous Read to Write transition Section
Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns
Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22
Various text edits
Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing
Changed ICCS and ICCR values
Added 256-Mbit AC Speed
Changed Program and Erase Spec
Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow
Chart
Revised Read While Buffered Programming Flow Chart
Revised Appendix A Write State Machine
Revised CFI Table 21 CFI Identification
Various text edits.
Various text clarifications, various text edits, block locking state diagram clarification, synchronous
read to write timing clarification, write to synchronous read timing clarification
Minor text edits
Changed Capacitance values
Changed Standby Current (typ), Power Down Current (typ), Erase Suspend Current (typ), and
Automatic Power Savings Current (typ)
Updated Transient Equialent Testing Load Circuit
April 2005
6
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet

6 Page









28F128L18 pdf, datenblatt
Intel StrataFlash® Wireless Memory (L18)
3.0 Package Information
3.1 VF BGA Packages
Figure 1. 64- and 128-Mbit, 56-Ball VF BGA Package Drawing and Dimensions
A1 Index
Mark
D
A1 Index
M a rk
S1
12345 678
A
B
C
ED
E
F
G
8 7 6 5 4 3 21
A
B
C
D
E
F
G
e
S2
b
Top View - Ball Side Down
Bottom View - Ball Side Up
A1
A2
Side View
www.DataSheet4U.com
Dimens ions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length (64Mb, 128Mb)
Package Body Width (64Mb, 128Mb)
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
A Seating
Plane
Y
Note: Drawing not to scale
Symbol
A
A1
A2
b
D
E
e
N
Y
S1
S2
Min
0.150
0.325
7.600
8.900
1.125
2.150
Millimeters
Nom Max
1.000
0.665
0.375
7.700
9.000
0.750
56
1.225
2.250
0.425
7.800
9.100
0.100
1.325
2.350
Notes
Min
0.0059
0.0128
0.2992
0.3504
0.0443
0.0846
Inches
Nom
0.0262
0.0148
0.3031
0.3543
0.0295
56
0.0482
0.0886
Max
0.0394
0.0167
0.3071
0.3583
0.0039
0.0522
0.0925
April 2005
12
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet

12 Page





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