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PDF MCP6284 Data sheet ( Hoja de datos )
| Número de pieza | MCP6284 | |
| Descripción | (MCP6281 - MCP6285) 5 MHz Rail-to-Rail Op Amp | |
| Fabricantes | Microchip Technology | |
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MCP6281/2/3/4/5
450 µA, 5 MHz Rail-to-Rail Op Amp
Features
• Gain Bandwidth Product: 5 MHz (typ.)
• Supply Current: IQ = 450 µA (typ.)
• Supply Voltage: 2.2V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with Chip Select (CS) (MCP6283)
• Dual with Chip Select (CS) (MCP6285)
Applications
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery-Powered Systems
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Description
The Microchip Technology Inc. MCP6281/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 5 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
margin. This family also operates from a single supply
voltage as low as 2.2V, while drawing 450 µA (typ.)
quiescent current. Additionally, the MCP6281/2/3/4/5
supports rail-to-rail input and output swing, with a
common mode input voltage range of VDD + 300 mV to
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
The MCP6285 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in Low-power mode.
The MCP6281/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.2V to 5.5V.
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Package Types
MCP6281
PDIP, SOIC, MSOP
NC 1
8 NC
VIN_ 2 -
7 VDD
VIN+ 3 +
6 VOUT
VSS 4
5 NC
MCP6281
SOT-23-5
VOUT 1
VSS 2
VIN+ 3
5 VDD
-
4 VIN–
MCP6281R
SOT-23-5
VOUT 1
VDD 2
VIN+ 3
5 VSS
-
4 VIN–
MCP6282
PDIP, SOIC, MSOP
VOUTA 1
8 VDD
VINA_ 2 - +
7 VOUTB
VINA+ 3
VSS 4
+ - 6 VINB_
5 VINB+
MCP6283
MCP6283
PDIP, SOIC, MSOP
SOT-23-6
NC 1
8 CS
VIN_ 2
VIN+ 3
VSS 4
-
+
7
6
VDD
VOUT
VOUT
VSS
1
2
5 NC VIN+ 3
6 VDD
- 5 CS
4 VIN_
MCP6284
PDIP, SOIC, TSSOP
VOUTA 1
14 VOUTD
VINA_ 2 - + + - 13 VIND_
VINA+ 3
VDD 4
12 VIND+
11 VSS
VINB+ 5
VINB_ 6
VOUTB 7
10 VINC+
- + + - 9 VINC_
8 VOUTC
MCP6285
PDIP, SOIC, MSOP
VOUTA/VINB+ 1
VINA_ 2
VINA+ 3
-+
+-
8 VDD
7 VOUTB
6 VINB_
VSS 4
5 CS
2004 Microchip Technology Inc.
DS21811D-page 1
1 page  
MCP6281/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
14%
12%
832 Samples
VCM = VSS
10%
8%
6%
4%
2%
0%
FIGURE 2-1:
Input Offset Voltage (mV)
Input Offset Voltage.
30%
25%
20%
832 Samples
VCM = VSS
TA = -40°C to +125°C
15%
10%
5%
0%
-10
-8 -6 -4 -2 0 2 4 6 8
Input Offset Voltage Drift (µV/°C)
10
FIGURE 2-4:
Input Offset Voltage Drift.
25%
20%
210 Samples
TA = +85°C
15%
10%
5%
0%
0
10 20 30 40 50 60 70 80 90 100
Input Bias Current (pA)
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FIGURE 2-2:
TA = +85 °C.
Input Bias Current at
300
VDD = 2.2V
250
200
150
100
50
0
-50
-100
-0.5
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0 0.5 1.0 1.5 2.0
Common Mode Input Voltage (V)
2.5
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.2V.
35%
210 Samples
30% TA = +125°C
25%
20%
15%
10%
5%
0%
FIGURE 2-5:
TA = +125 °C.
Input Bias Current (pA)
Input Bias Current at
300
VDD = 5.5V
250
200
150
100
50
0
-50
-100
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
2004 Microchip Technology Inc.
DS21811D-page 5
5 Page 
4.0 APPLICATION INFORMATION
The MCP6281/2/3/4/5 family of op amps is manufac-
tured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for low-
cost, low-power and general purpose applications.
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/2/3/4/5 ideal for
battery-powered applications.
4.1 Rail-to-Rail Inputs
The MCP6281/2/3/4/5 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
6
VDD = 5.0V
5 G = +2 V/V
4
VIN VOUT
3
2
1
0
-1 -15 -14 -13 -12 -11 -10
-9
-8
-7
-6
-5
Time (1 ms/div)
FIGURE 4-1:
The MCP6281/2/3/4/5 Show
No Phase Reversal.
The input stage of the MCP6281/2/3/4/5 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. With this
topology, the device
www.DataSheeatb4Uov.ceomVDD and 0.3V
operates with
below VSS. The
VCM
Input
up to
Offset
0.3V
Volt-
age (VOS) is measured at VCM = VSS – 0.3V and
VDD + 0.3V to ensure proper operation.
Input voltages that exceed the absolute maximum
voltage (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.
2004 Microchip Technology Inc.
MCP6281/2/3/4/5
–
RIN MCP628X
VIN +
VOUT
RIN
≥
-(--M-----a---x---i-m-----u---m-----e---x---p---e---c--t--e--d-----V----I---N----)----–----V----D-----D--
2 mA
RI
N
≥
-V---S----S----–-----(--M-----i--n---i--m----u---m------e--x---p---e---c--t--e---d-----V----I--N-----)
2 mA
FIGURE 4-2:
Resistor (RIN).
Input Current Limiting
4.2 Rail-to-Rail Output
The output voltage range of the MCP6281/2/3/4/5 op
amp is VDD – 15 mV (min.) and VSS + 15 mV (max.)
when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-16 for more information.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitive load.
–
MCP628X
VIN +
RISO
CL
VOUT
FIGURE 4-3:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
DS21811D-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP6284.PDF ] | |
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