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ADP150 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP150
Beschreibung 150 mA CMOS Linear Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADP150 Datasheet, Funktion
FEATURES
Ultra low noise: 9 μV rms, independent of VOUT
No additional noise bypass capacitor required
Stable with 1 μF ceramic input and output capacitors
Maximum output current: 150 mA
Input voltage range: 2.2 V to 5.5 V
Low quiescent current
IGND = 10 μA with zero load
Low shutdown current: <1 μA
Low dropout voltage: 105 mV @ 150 mA load
Initial output voltage accuracy: ±1%
Up to 14 fixed output voltage options: 1.8 V to 3.3 V
PSRR performance of 70 dB at 10 kHz
Current limit and thermal overload protection
Logic-controlled enable
5-lead TSOT package
4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
RF, PLL, VCO, and clock power supplies
GENERAL DESCRIPTION
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The ADP150 is an ultralow noise (9 μV), low dropout, linear
regulator that operates from 2.2 V to 5.5 V and provides up to
150 mA of output current. The low 105 mV dropout voltage at
150 mA load improves efficiency and allows operation over a
wide input voltage range.
Using an innovative circuit topology, the ADP150 achieves ultralow
noise performance without the necessity of an additional noise
bypass capacitor, making it ideal for noise sensitive analog and
RF applications. The ADP150 also achieves ultralow noise
performance without compromising PSRR or line and load
transient performance. The ADP150 offers the best combination
of ultralow noise and quiescent current consumption to maximize
battery life in portable applications.
Ultralow Noise,
150 mA CMOS Linear Regulator
ADP150
TYPICAL APPLICATION CIRCUITS
VIN = 2.3V
CIN
1µF
ON
OFF
1 VIN VOUT 5
2 GND
VOUT = 1.8V
COUT
1µF
3 EN
NC 4
NC = NO CONNECT
Figure 1. 5-Lead TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V
CIN
1µF
ON
OFF
12
VIN VOUT
TOP VIEW
(Not to Scale)
VOUT = 1.8V
A COUT
1µF
EN GND B
Figure 2. 4-Ball WLCSP with Fixed Output Voltage, 1.8 V
The ADP150 is specifically designed for stable operation with
tiny 1 μF ± 30% ceramic input and output capacitors to meet
the requirements of high performance, space-constrained
applications.
The ADP150 is available in 14 fixed output voltage options,
ranging from 1.8 V to 3.3 V.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP150 is available in tiny
5-lead TSOT and 4-ball, 0.4 mm pitch WLCSP packages for the
smallest footprint solution to meet a variety of portable power
applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






ADP150 Datasheet, Funktion
ADP150
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VIN 1
5 VOUT
ADP150
GND 2 TOP VIEW
(Not to Scale)
EN 3
4 NC
NC = NO CONNECT
Figure 3. 5-Lead TSOT Pin Configuration
12
A VIN
VOUT
TOP VIEW
(Not to Scale)
B EN
GND
Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. 5-Lead TSOT Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN
Regulator Input Supply. Bypass VIN to
GND with a 1 μF or greater capacitor.
2 GND Ground.
3 EN
Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
4 NC
No Connect. Not connected internally.
5
VOUT
Regulated Output Voltage. Bypass VOUT
to GND with a 1 μF or greater capacitor.
Table 6. 4-Ball WLCSP Pin Function Descriptions
Pin No. Mnemonic Description
A1 VIN
Regulator Input Supply. Bypass VIN to
GND with a 1 μF or greater capacitor.
A2 VOUT
Regulated Output Voltage. Bypass VOUT
to GND with a 1 μF or greater capacitor.
B1 EN
Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
B2 GND
Ground.
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Rev. 0 | Page 6 of 20

6 Page









ADP150 pdf, datenblatt
ADP150
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP150 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO control loop. A minimum of 1 μF
capacitance with an ESR of 1 Ω or less is recommended to
ensure the stability of the ADP150. The transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP150 to large changes in the load current.
Figure 27 and Figure 28 show the transient responses for output
capacitance values of 1 μF and 4.7 μF, respectively.
T
IOUT
1mA TO 150mA LOAD STEP
1
2
VOUT
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the ADP150,
as long as they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
Figure 29 depicts the capacitance vs. the voltage bias characteristic
of a 0402, 1 μF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
VIN = 3.7V
VOUT = 3.3V
CH1 100mA CH2 50mV
M1.0µs
A CH1 100mA
T 716.000µs
Figure 27. Output Transient Response, COUT = 1 μF
0.6
0.4
0.2
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1
T
IOUT
1mA TO 150mA LOAD STEP
2
VOUT
VIN = 3.7V
VOUT = 3.3V
CH1 100mA CH2 50mV
M1.0µs
A CH1 108mA
T 240.000ns
Figure 28. Output Transient Response, COUT = 4.7 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance is encountered. If greater than
1 μF of output capacitance is required, increase the input capacitor
to match the output capacitor.
0
02468
BIAS VOLTAGE (V)
Figure 29. Capacitance vs. Voltage Bias Characteristic
10
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
the CBIAS is 0.94 μF at 1.8 V, as shown in Figure 29.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
Rev. 0 | Page 12 of 20

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