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PDF LTC2267-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2267-12 | |
| Descripción | (LTC226x-12) 125Msps/105Msps/ 80Msps Low Power Dual ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2268-12/
LTC2267-12/LTC2266-12
12-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
FEATURES
n 2-Channel Simultaneous Sampling ADC
n 70.6dB SNR
n 88dB SFDR
n Low Power: 292mW/238mW/200mW Total,
146mW/119mW/100mW per Channel
n Single 1.8V Supply
n Serial LVDS Outputs: 1 or 2 Bits per Channel
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full Power Bandwidth S/H
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit and 12-Bit Versions
n 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multichannel Data Acquisition
n Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
DESCRIPTION
The LTC®2268-12/LTC2267-12/LTC2266-12 are 2-channel,
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSBRMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
TYPICAL APPLICATION
1.8V
VDD
1.8V
OVDD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
S/H
S/H
12-BIT
ADC CORE
12-BIT
ADC CORE
PLL
DATA
SERIALIZER
OUT1A
OUT1B
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226812 TA01
SERIALIZED
LVDS
OUTPUTS
LTC2268-12, 125Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 TA01b
22687612f
1
1 page  
LTC2268-12/
LTC2267-12/LTC2266-12
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
TYP
MAX UNITS
VIH High Level Input Voltage
VDD =1.8V
l 1.3
V
VIL Low Level Input Voltage
VDD =1.8V
l
0.6 V
IIN Input Current
VIN = 0V to 3.6V
l –10
10 μA
CIN Input Capacitance
3 pF
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND
IOH Logic High Output Leakage Current
COUT Output Capacitance
DIGITAL DATA OUTPUTS
VDD =1.8V, SDO = 0V
SDO = 0V to 3.6V
l –10
200
3
10
Ω
μA
pF
VOD Differential Output Voltage
100Ω Differential Load, 3.5mA Mode l
247
350
454
mV
100Ω Differential Load, 1.75mA Mode l
125
175
250
mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.25 1.375
100Ω Differential Load, 1.75mA Mode l 1.125 1.25 1.375
V
V
RTERM On-Chip Termination Resistance
Termination Enabled, OVDD =1.8V
100 Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2268-12
LTC2267-12
LTC2266-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD
OVDD
IVDD
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
Analog Supply Current Sine Wave Input
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
l 146 165
116 129
96 109
V
V
mA
IOVDD
Digital Supply Current 2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
16 20
30 34
16 19
29 33
15 18
29 32
mA
mA
PDISS Power Dissipation
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
292 333
317 358
238 266
261 292
200 229
225 254
mW
mW
PSLEEP Sleep Mode Power
1 1 1 mW
PNAP Nap Mode Power
70 70 70 mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
20
20
20 mW
(No Increase for Sleep Mode)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2268-12
LTC2267-12
LTC2266-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency
(Notes 10, 11)
l5
125 5
105 5
80 MHz
tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l 3.8 4 100 4.52 4.76 100 5.93 6.25 100
l2
4 100 2 4.76 100 2 6.25 100
ns
ns
tENCH
Analog Supply Current
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l 3.8 4 100 4.52 4.76 100 5.93 6.25 100
l2
4 100 2 4.76 100 2 6.25 100
ns
ns
tAP Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
22687612f
5
5 Page 
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2268-12: Integral
Nonlinearity (INL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226812 G01
LTC2268-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226812 G02
LTC2268-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 G04
LTC2268-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 G07
LTC2268-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 G05
LTC2268-12: Shorted Input
Histogram
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
2041
2042
2043
2044
OUTPUT CODE
2045
226812 G08
LTC2268-12: 8k Point FFT,
fIN = 5MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 G03
LTC2268-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226812 G06
LTC2268-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
125Msps
72
71
70
69
68
67
66
0 50 100 150 200 250 300 350
INPUT FREQUENCY (MHz)
226812 G09
22687612f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2267-12.PDF ] | |
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