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PDF AD9116 Data sheet ( Hoja de datos )
| Número de pieza | AD9116 | |
| Descripción | 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters | |
| Fabricantes | Analog Devices | |
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Data Sheet
Dual Low Power, 8-/10-/12-/14-Bit
TxDAC Digital-to-Analog Converters
AD9114/AD9115/AD9116/AD9117
FEATURES
Power dissipation @ 3.3 V, 20 mA output
191 mW @ 10 MSPS
232 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
86 dBc @ 1 MHz output
85 dBc @ 10 MHz output
AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz
Differential current outputs: 2 mA to 20 mA
2 on-chip auxiliary DACs
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package
APPLICATIONS
Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
GENERAL DESCRIPTION
The AD9114/AD9115/AD9116/AD9117 are pin-compatible
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of commu-
nication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9114/AD9115/AD9116/AD9117
make them well suited for portable and low power applications.
PRODUCT HIGHLIGHTS
1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply;
total power consumption reduces to 225 mW at 100 MSPS.
Sleep and power-down modes are provided for low power
idle periods.
2. CMOS Clock Input. High speed, single-ended CMOS clock
input supports a 125 MSPS conversion rate.
3. Easy Interfacing to Other Components. Adjustable output
common mode from 0 V to 1.2 V allows for easy interfacing
to other components that accept common-mode levels
greater than 0 V.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2013 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD9114/AD9115/AD9116/AD9117
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY, AVDD = DVDDIO =
CVDD = 3.3 V
Differential Nonlinearity (DNL)
Precalibration
Postcalibration
Integral Nonlinearity (INL)
Precalibration
Postcalibration
ACCURACY, AVDD = DVDDIO =CVDD =
1.8 V
Differential Nonlinearity (DNL)
Precalibration
Postcalibration
Integral Nonlinearity (INL)
Precalibration
Postcalibration
MAIN DAC OUTPUTS
Offset Error
Gain Error Internal Reference
Full-Scale Output Current1
AVDD = 3.3 V
AVDD = 1.8 V
Output Common-Mode Level
(8 mA CMLx Pin)
Output Compliance Range
AVDD = 3.3 V, 8 mA Output
Common Mode Level = −0.5
Common Mode Level = 0
Common Mode Level = +1.2
Output Resistance
Crosstalk, Q DAC to I DAC
(fOUT = 30 MHz)
Crosstalk, Q DAC to I DAC
(fOUT = 60 MHz)
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AD9114
Min Typ
Max
8
AD9115
Min Typ
Max
10
AD9116
Min Typ
Max
12
AD9117
Min Typ Max
14
Unit
Bits
±0.02
±0.02
±0.03
±0.03
±0.06
±0.04
±0.19
±0.07
±0.4
±0.2
±0.68
±0.42
±1.4 LSB
±0.6 LSB
±1.2 LSB
±0.6 LSB
±0.02
±0.01
±0.08
±0.06
±0.5
±0.2
±0.04
±0.02
±0.2
±0.1
±0.5
±0.3
−1 +1 −1 +1 −1
−2 +2 −2 +2 −2
28
2
−0.5 0
20 2
8
82
+1.2 −0.5 0
20 2
8
82
+1.2 −0.5 0
±1.8
±1.0
±1.8
±1.1
+1 −1
+2 −2
20 2
8
82
+1.2 −0.5 0
LSB
LSB
LSB
LSB
+1 mV
+2 % of FSR
20 mA
8 mA
+1.2 V
−0.9
−0.4
0.8
200
95
76
−0.1 −0.9
+0.4 −0.4
1.5 0.8
200
95
76
−0.1 −0.9
+0.4 −0.4
1.5 0.8
200
95
76
−0.1 −0.9
+0.4 −0.4
1.5 0.8
200
95
76
−0.1 V
+0.4 V
1.5 V
MΩ
dB
dB
0 0 0 0 ppm/°C
±40 ±40 ±40 ±40 ppm/°C
±25 ±25 ±25 ±25 ppm/°C
Rev. C | Page 5 of 52
5 Page 
Data Sheet
AD9114/AD9115/AD9116/AD9117
Pin No.
29
30
31
32
33
34
35
36
37
38
39
40
Mnemonic
IOUTN
RLIN
CMLI
FSADJQ/AUXQ
FSADJI/AUXI
REFIO
RESET/PINMD
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
DB7 (MSB)
DB6
EP (EPAD)
Description
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale
current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see
the Retimer section.
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down
to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement
input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. C | Page 11 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9116.PDF ] | |
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