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AD9122 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9122
Beschreibung Digital-to-Analog Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9122 Datasheet, Funktion
Dual, 16-Bit, 1230 MSPS,
TxDAC+ Digital-to-Analog Converter
AD9122
FEATURES
Flexible LVDS interface allows word, byte, or nibble load
Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Integrated 2×/4×/8× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain, dc offset, and phase adjustment for sideband
suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS,
full operating conditions
72-lead, exposed paddle LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9122 is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a sample rate of 1230 MSPS,
permitting multicarrier generation up to the Nyquist frequency.
The AD9122 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod-
ulation, and gain and offset compensation. The DAC outputs
are optimized to interface seamlessly with analog quadrature
modulators, such as the ADL537x F-MOD series from Analog
Devices, Inc. A 4-wire serial port interface provides for program-
ming/readback of many internal parameters. Full-scale output
current can be programmed over a range of 8.7 mA to 31.7 mA.
The AD9122 comes in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies (IF).
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. Current outputs are easily configured for various single-
ended or differential circuit topologies.
4. Flexible LVDS digital interface allows the standard 32-wire
bus to be reduced to one-half or one-quarter of the width.
COMPANION PRODUCTS
IQ Modulators: ADL5370, ADL537x family
IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family
Clock Drivers: AD9516, AD951x family
Voltage Regulator Design Tool: ADIsimPower
Additional companion products on the AD9122 product page
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC fIF
DIGITAL
BASEBAND
PROCESSOR
2
SIN
COS
2
2/4 I DAC
2/4 Q DAC
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
LO – fIF
ANTIALIASING
FILTER
AQM PA
LO
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.






AD9122 Datasheet, Funktion
AD9122
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise
noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
CMOS OUTPUT LOGIC LEVEL
Output VOUT Logic High
Output VOUT Logic Low
LVDS RECEIVER INPUTS1
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK Frequency (PLL Mode)
REFCLK Frequency (SYNC Mode)
SERIAL PORT INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWL)
Setup Time, SDIO to SCLK (tDS)
Hold Time, SDIO to SCLK (tDH)
Data Valid, SDO to SCLK (tDV)
Setup Time, CS to SCLK (tDCSB)
Test Conditions/Comments
Min Typ
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V, 3.3 V
1.2
1.6
2.0
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V, 2.5 V, 3.3 V
Applies to data, DCI, and FRAME inputs
See Table 5
1.4
1.8
2.4
825
−100
80
20
Self-biased input, ac-coupled
100
1230
500
1.25
100
1 GHz ≤ fVCO ≤ 2.1 GHz
15.625
See the Multichip Synchronization section 0
for conditions
500
1.25
40
1.9
0.2
2.3
1.4
Max
0.6
0.8
0.4
1675
+100
120
Unit
V
V
V
V
V
V
V
V
V
mV
mV
mV
Ω
2000
2000
600
600
mV
V
MHz
mV
V
MHz
MHz
MHz
12.5 ns
12.5 ns
ns
ns
ns
ns
1 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted.
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation (With or Without Modulation)
2× Interpolation (With or Without Modulation)
4× Interpolation (With or Without Modulation)
8× Interpolation (With or Without Modulation)
Inverse Sinc
Fine Modulation
Value
64
135
292
608
20
8
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Rev. B | Page 6 of 60

6 Page









AD9122 pdf, datenblatt
AD9122
–69 fDATA = 250MSPS
–70 fDATA = 400MSPS
–71
–72
–73
–74
–75
–76
–77
–78
–79
0
50 100 150 200 250 300 350 400 450
fOUT (MHz)
Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, IFS = 20 mA
–60 fDATA = 100MSPS
fDATA = 200MSPS
–65
–70
–75
–80
–85
0
50 100 150 200 250 300 350 400 450
fOUT (MHz)
Figure 11. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, IFS = 20 mA
–60
fDATA = 100MSPS
fDATA = 150MSPS
–65
–70
–75
–80
–85
–90
–95
0
100 200 300 400 500 600 700
fOUT (MHz)
Figure 12. Highest Digital Spur vs. fOUT over fDATA, 8× Interpolation,
Digital Scale = 0 dBFS, IFS = 20 mA
2× INTERPOLATION,
SINGLE-TONE SPECTRUM,
ffDOAUTTA==10215M0MHSzPS,
START 1.0MHz
#RES BW 10kHz
VBW 10kHz
STOP 500.0MHz
SWEEP 6.017s (601 PTS)
Figure 13. Single-Tone Spectrum, 2× Interpolation,
fDATA = 250 MSPS, fOUT = 101 MHz
4× INTERPOLATION,
SINGLE-TONE SPECTRUM,
ffDOAUTTA==15210M0MHSzPS,
START 1.0MHz
#RES BW 10kHz
VBW 10kHz
STOP 800.0MHz
SWEEP 9.634s (601 PTS)
Figure 14. Single-Tone Spectrum, 4× Interpolation,
fDATA = 200 MSPS, fOUT = 151 MHz
8× INTERPOLATION,
SINGLE-TONE SPECTRUM,
ffDOAUTTA==13110M0MHSzPS,
START 1.0MHz
#RES BW 10kHz
VBW 10kHz
STOP 800.0MHz
SWEEP 9.634s (601 PTS)
Figure 15. Single-Tone Spectrum, 8× Interpolation,
fDATA = 100 MSPS, fOUT = 131 MHz
Rev. B | Page 12 of 60

12 Page





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