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T80C5112 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer T80C5112
Beschreibung 8-bit Microcontroller
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 30 Seiten
T80C5112 Datasheet, Funktion
8-bit Microcontroller with A/D converter
T80C5112
1. Description
The T80C5112 is a high performance ROM/OTP version
of the 80C51 8-bit microcontroller.
The T80C5112 retains all the features of the standard
80C51 with 8 Kbytes ROM/OTP program memory, 256
bytes of internal RAM, a 8-source , 4-level interrupt
system, an on-chip oscillator and two timer/counters.
The T80C5112 is dedicated for analog interfacing
applications. For this, it has an 10-bit, 8 channels A/D
converter and a five channels Programmable Counter
Array.
In addition, the T80C5112 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial channel that facilitates multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed
improvement mechanism. The X2 feature allows to keep
the same CPU power at a divided by two oscillator
frequency.
The fully static design of the T80C5112 allows to reduce
system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T80C5112 has 3 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
The T80C5112 is proposed in 48/52 pin count packages
with Port 0 and Port 2 (address / data busses).
2. Features
· 80C51 Compatible
· Crystal or ceramic oscillator with hardware set
· Five I/O ports
up (32 KHz or 33/40 MHz)
· Two 16-bit timer/counters
· Internal RC oscillator (12 MHz)
· 256 bytes RAM
· Programmable prescaler
· 8Kbytes ROM/OTP program memory with 64 bytes
www.DataSheete4nUc.cryopmtion array and 3 security levels.
· Active oscillator during reset defined by hardware
set up
· High-Speed Architecture
· Timer 0 subclock mode for Real Time Clock.
· Programmable counter array with High speed output,
· 33MHz @ 5V (66 MHz equivalent)
Compare / Capture, Pulse Width Modulation and
· 20MHz @ 3V (40 MHz equivalent)
Watchdog timer capabilities
· X2 Speed Improvement capability (6 clocks/ · Interrupt Structure with:
·
·
machine cycle)
10-bit, 8 channels A/D converter
Hardware Watchdog Timer with integrated low
power oscillator (20m A) and Reset-Out
·
· 8 Interrupt sources,
· 4 interrupt priority levels
Power Control modes:
· Programmable I/O mode: standard C51, input only,
· Idle mode
push-pull, open drain.
· Power-down mode
· Asynchronous port reset, Power On Reset
· Power-off Flag, Power fail detect, Power on Reset
· Full duplex Enhanced UART with baud rate generator · Power supply: 2.7 to 5.5V
· SPI, master/slave mode
· Temperature ranges: Commercial (0 to 70C) and
Industrial (-40 to 85 C), optionnal extented
· Dual system clock
· Package:LQFP48 (body 7*7*1.4mm), PLCC52
Rev. B - November 10, 2000
Preliminary
1






T80C5112 Datasheet, Funktion
T80C5112
P0.0-P0.7
P2.0-P2.7
RST
ALE
PSEN
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EA
XTAL1
XTAL2
I/O
AIN3 (P4.3): A/D converter input 3
INT1: External interrupt 1
I/O
AIN4 (P4.4): A/D converter input 4
MISO: Master IN, Slave OUT of the SPI controller
I/O
AIN5 (P4.5): A/D converter input 5
MOSI: Master OUT, Slave IN of the SPI controller
I/O
AIN6 (P4.6): A/D converter input 6
SPSCK: Clock I/O of the SPI controlle
I/O AIN7 (P4.7): A/D converter input 7
X X I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them ßoat and can be used as high impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during access to external program
and data memory. In this application, it uses strong internal pull-up when emitting
1s.
X X I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
XX
I RST: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC. If the hardware watchdog reaches its
time-out, the reset pin becomes an output during the time the internal reset is
activated.
X X O Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each
access to external data memory. ALE can be disabled by setting SFRÕs AUXR.0
bit. With this bit set, ALE will be inactive during internal fetches.
X X O Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
XX
I External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations 0000H and 1FFFH . If
EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. EA must be held low
for ROMless devices. If security level 1 is programmed, EA will be internally
latched on Reset.
X
I
XTAL1 : Input to the inverting oscillator amplifier and input to the internal
clock generator circuits, selected by hardware set upb
X
O
XTAL2 : Output from the inverting oscillator amplifier, selected by hardware
set up
a. Hardware set up :
+Configuration bits programmed with the code for ROM version
+Configuration bits for EPROM version
b. Hardware set up :
+Configuration bits programmed with the code for ROM version
+Configuration bits for EPROM version
6 Rev. B - November 10, 2000
Preliminary

6 Page









T80C5112 pdf, datenblatt
T80C5112
Bit
Number
4
3
2
1
0
Bit Description
Mnemonic
RST_OSC Selected oscillator at reset
This bit is used to deÞne the value of some bits controlling the oscillator activity at reset:
1: The crystal oscillator is sectected and active
0: The RC oscillator is selected; it is also active if the WDRC is inactive.
XT_SP Crystal oscillator speed
This bit is used to deÞne the performance of the crystal oscillator.
1: High speed, up to 33 MHz
0: Low speed, low power, optimised for 32 kHz.
EXT_RST External Reset
This bit deÞnes the behavior of the P3.6/RST pin
1: P3.6/RST is the reset pin
0: P3.6/RST is an input pin
OSCC_OFF Control for watchdog RC oscillator
This bit is used to switch the watchdog RC oscillator and the watchdog source
1: WDRC oscillator is off; the watchdog is clocked by the main oscillator.
0: WDRC oscillator is on and clock the watchdog
- Reserved
The value read from this bit is indeterminate. Do not reset this bit.
Initial value after erasing : 1111 111X
6.6.2. Clock control register
The clock control register is used to define the clock system behavior
OSCCON - Clock Control Register (86h)
765
---
4
-
32
- SCLKT0
Bit Bit
Description
Number Mnemonic
7 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
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-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 Sub Clock Timer0
SCLKT0
Cleared by software to select T0 pin
Set by software to select T0 Sub Clock
1 OSCBEN Enable RC oscillator
This bit is used to enable the high speed RC oscillator
0: The oscillator is disabled
1: The oscillator is enabled.
0 OSCAEN Enable crystal oscillator
This bit is used to enable the crystal oscillator
0: The oscillator is disabled
1: The oscillator is enabled.
Reset Value = 0XXX X0 "RST_OSC" "RST_OSC" b
Not bit addressable
1
OSCBEN
0
OSCAEN
12 Rev. B - November 10, 2000
Preliminary

12 Page





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