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PDF FX-402 Data sheet ( Hoja de datos )
| Número de pieza | FX-402 | |
| Descripción | Low Jitter VCSO Frequency Translator | |
| Fabricantes | Vectron International | |
| Logotipo |  |
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FX-402
Low Jitter Frequency Translator
Previous Part Number FX-427
FX-402
Description
The FX-402 is a precision quartz-based frequency translator used to translate 1 to 4 selected input clocks as low as 8 kHz to an
integer multiple as high as 850 MHz. The FX-402’s superior jitter performance is achieved through the filtering action of the on-
board voltage-controlled SAW oscillator (VCSO) and integrated loop filter. Two low-jitter outputs are provided. Monitoring and
control functionality are also standard features.
Features
Applications
• Quartz-based PLL for Ultra-Low Jitter
• Frequency Translation up to 850 MHz
• Accepts 4 externally-muxed clock inputs
• LVCMOS/LVDS/LVPECL Inputs Compatible
• Differential LVPECL Outputs
• Lock Detect
• Output Disable
• 20.3 x 13.7 x 5.1 mm surface mount package
www.D• aCtaoSmhepelita4nUt.ctoomEC RoHS Directive
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• Test Equipment
Block Diagram
FIN
1
FIN
2
FIN
3
FIN
4
SEL0 (1)
SEL1 (2)
VCC
(14)
÷FIN
(13)
LD
(7)
Phase
Detector
& LD
VMON
(5)
Loop Filter
VCSO
μ Controller
÷÷
GND
(3, 12)
OD
(6)
Figure 1. Functional block diagram
(8)
FOUT
1
(9)
CFOUT
1
(10)
FOUT
2
(11)
CFOUT
2
Page 1 of 8
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 8/13/2009
1 page  
Pin Configuration
Pin #
1
2
3
4
5
Symbol
SEL0
SEL1
GND
I/O
I
I
GND
VMON O
6 OD I
7 LD O
8 FOUT1
9 CFOUT1
www.Data1S0heet4U.comFOUT2
11 CFOUT2
12 GND
O
O
O
O
GND
Figure 6. Pin Configuration
Table 7. Pin Functions
Level
LVCMOS
Frequency Select - see table 3
Function
LVCOMS
Supply
LVCMOS
LVCMOS
LCPECL
LVPECL
Frequency Select – see table 3
Case and Electrical Ground
Not present
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input fre-
quency may be out of range if the voltage exceeds these levels
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Lock Detect
Locked = Logic “1”
Loss of Lock = Logic “0”
Frequency Output – Primary
Complimentary Frequency Output - Primary
LVPECL
LVPECL
Supply
Divided-Down VCSO/VCXO Output, or Disabled
Complimentary Divided-Down VCSO/VCXO Output, or Disabled
Case and Electrical Ground
13 FIN I
LVCMOS or
LVPECL
Input Frequency – AC Coupled
14
VCC VCC
Supply
Power Supply Voltage (3.3 V ±5%)
LVCMOS input signal levels are valid for input frequencies < 100 MHz.
SEL 0
0
0
1
1
SEL 1
0
1
0
1
Table 8. Control Logic (LVCMOS)
CLock Input
FIN
1
FIN
2
FIN3
FIN
4
Page 5 of 8
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 8/13/2009
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet FX-402.PDF ] | |
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