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WV3HG264M72EER-PD4 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WV3HG264M72EER-PD4
Beschreibung 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 11 Seiten
WV3HG264M72EER-PD4 Datasheet, Funktion
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, SO-DIMM, w/PLL
FEATURES
Registered 200-pin (SO-DIMM), Small-Outline dual
in-line memory module
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Differential clock inputs (CK, CK#)
Programmable CAS# latency (CL): 3, 4, 5*, and 6*
Posted CAS# additive latency: 0, 1, 2, 3 and 4
On-die termination (ODT)
7.8µs average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Utilizes 512Mb DDR2 SDRAM components
Auto & self refresh (64ms: 8,192 cycle refresh)
wwwG.DoaltdaSehdegeet4cUo.ncotamcts
Dual Rank
RoHS compliant
JEDEC proposed Pin-out
Package
• 200 Pin SO-DIMM: 30.00mm (1.181") TYP.
DESCRIPTION
The WV3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit DDR2 Synchronous
DRAMs in FBGA packages, mounted on a 200-pin SO-
DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
April 2006
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WV3HG264M72EER-PD4 Datasheet, Funktion
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
806
ICC0* Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
ICC1*
ICC2P*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD
TBD
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD
ICC2N**
ICC3P**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING Slow PDN Exit MRS(12) = 1
TBD
TBD
TBD
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
www.DatatRSAhSmeaext(4ICUC.)c, toRmP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
TBD
TBD
TBD
ICC6** Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD
ICC7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
TBD
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
665 534 403 Units
1,337 1,292 1,292 mA
1,472 1,427 1,427 mA
644 644 644 mA
1,130 1,040 1,040 mA
1,220 1,130 1,130 mA
1,040 1,040 1,040
716 716 716
mA
mA
1,490 1,400 1,400 mA
1,832 1,652 1,562 mA
1,877 1,697 1,562 mA
3,200 3,020 3,020 mA
144 144 144 mA
2,552 2,552 2,552 mA
April 2006
Rev. 2
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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