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WV3HG2128M72AER-D6 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WV3HG2128M72AER-D6
Beschreibung 2GB - 2x128Mx72 DDR2 SDRAM REGISTERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 11 Seiten
WV3HG2128M72AER-D6 Datasheet, Funktion
White Electronic Designs WV3HG2128M72AER-D6
ADVANCED*
2GB – 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-4200 and PC2-3200
Utilizes 533 and 400 Mb/s DDR2 SDRAM
components
VCC = VCCQ = 1.8V± 0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Product is lead-free
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Dual Rank
Package option
• 240 Pin DIMM
• PCB – 29.97mm (1.18")
DESCRIPTION
The WV3HG2128M72AER is a 128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of thirty six 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
September
2005 Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WV3HG2128M72AER-D6 Datasheet, Funktion
White Electronic Designs WV3HG2128M72AER-D6
ADVANCED*
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
534 403 Units
IDD0* Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2284 2284
mA
IDD1* Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus input
are switching; Data pattern is same as IDD6W
2554
2554
mA
IDD2P**
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
988 988 mA
IDD2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
1780
1780
mA
IDD2N**
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1960 1960
mA
IDD3P**
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
1780
1132
1780
1132
mA
mA
IDD3N**
Active standby current;
All banks open; tCK = tCK(IDD), tRC = tRC(IDD); tRAS = tRASmax(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
www.DataSbhuseientp4uUts.acroemSWITCHING
IDD4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
IDD5** Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD6** Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
IDD7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data bus imputs are switching.
Notes:
IDD specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
* Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
2500
2824
2914
5740
288
4804
2500
2644
2734
5740
288
4804
mA
mA
mA
mA
mA
mA
September
2005 Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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