WV3EG32M64ETSU-D3 Datasheet PDF - White Electronic Designs
| Part Number | WV3EG32M64ETSU-D3 | |
| Description | 256MB - 32Mx64 DDR SDRAM UNBUFFERED | |
| Manufacturers | White Electronic Designs | |
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White Electronic Designs
WV3EG32M64ETSU-D3
ADVANCED*
256MB – 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
• VCC = VCCQ = +2.5V ±0.2V
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
DESCRIPTION
The WV3EG32M64ETSU is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
July 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs
WV3EG32M64ETSU-D3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating one bank active-
precharge current;
Operating one bank active-
read-precharge current;
Precharge power-down
current;
Precharge quiet standby
current;
Precharge standby current;
Active power-down current;
Active standby current;
Operating burst write current;
Operating burst read current;
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Burst auto refresh current;
Self refresh current;
Operating bank interleave
read current;
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2F
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
Conditions
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS =
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address businputs are SWITCHING; Data pattern is same as IDD4W
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address
bus inputsare STABLE; Data bus inputs are FLOATING
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH,
CS - is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-
1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for
detailed timing conditions
DDR333@
CL = 2.5
720
920
24
160
200
280
440
1280
1280
1360
24
2240
Note: These specifications apply to modules built with Samsung components only.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
July 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WV3EG32M64ETSU-D3 electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WV3EG32M64ETSU-D3.PDF Datasheet ] | |
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