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26DF081A Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer 26DF081A
Beschreibung AT26DF081A
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 36 Seiten
26DF081A Datasheet, Funktion
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
70 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
Optimized Physical Sectoring for Code Shadowing and Code + Data Storage
Applications
– One 32-Kbyte Top Boot Sector
– Two 8-Kbyte Sectors
– One 16-Kbyte Sector
– Fifteen 64-Kbyte Sectors
Individual Sector Protection for Program/Erase Protection
Hardware Controlled Locking of Protected Sectors
Flexible Programming Options
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 11 µA Deep Power-down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 200-mil wide)
ww1w..DataDSheeset4cUr.ciopmtion
The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF081A have been opti-
mized to meet the needs of today’s code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
8-megabit
2.7-volt Only
Serial Firmware
DataFlash®
Memory
AT26DF081A
Preliminary
3600A–DFLASH–11/05






26DF081A Datasheet, Funktion
Table 6-1. Command Listing
Command
Opcode
Address Bytes Dummy Bytes Data Bytes
Read Commands
Read Array
0Bh 0000 1011
3
1 1+
Read Array (Low Frequency)
03h 0000 0011
3
0 1+
Program and Erase Commands
Block Erase (4 Kbytes)
20h 0010 0000
3
0
0
Block Erase (32 Kbytes)
52h 0101 0010
3
0
0
Block Erase (64 Kbytes)
D8h 1101 1000
3
0
0
Chip Erase
60h 0110 0000
0
0
0
C7h 1100 0111
0
0
0
Byte/Page Program (1 to 256 Bytes)
02h 0000 0010
3
0 1+
Sequential Program Mode
ADh 1010 1101
AFh 1010 1111
3, 0(1)
3, 0(1)
0
0
1
1
Protection Commands
Write Enable
06h 0000 0110
0
0
0
Write Disable
04h 0000 0100
0
0
0
Protect Sector
36h 0011 0110
3
0
0
Unprotect Sector
39h 0011 1001
3
0
0
Read Sector Protection Registers
3Ch 0011 1100
3
0 1+
Status Register Commands
Read Status Register
05h 0000 0101
0
0 1+
Write Status Register
01h 0000 0001
0
0
1
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Read Manufacturer and Device ID
9Fh 1001 1111
0
0 1 to 4
Deep Power-down
B9h 1011 1001
0
0
0
Resume from Deep Power-down
ABh 1010 1011
0
0
0
Note:
1. Three address bytes are only required for the first operation to designate the address to start programming at. Afterwards,
the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require
clocking in of the opcode and the data byte until the Sequential Program Mode has been exited.
6 AT26DF081A [Preliminary]
3600A–DFLASH–11/05

6 Page









26DF081A pdf, datenblatt
www.DataSheet4U.com
If the address specified by A23 - A0 points to a memory location within a sector that is in the pro-
tected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase
sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 18
through 15) at one time. Therefore, in order to erase a larger block that may span more than one
sector, all of the sectors in the span must be in the unprotected state. If one of the physical sec-
tors within the span is in the protected state, then the device will ignore the Block Erase
command and will return to the idle state once the CS pin is deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle
aborts due to an incomplete address being sent or because a memory location within the region
to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte loca-
tion fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the
Status Register.
Figure 8-5. Block Erase
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
26 27 28 29 30 31
OPCODE
ADDRESS BITS A23-A0
CCCCCCCCAAAAAA
MSB
MSB
AAAAAA
HIGH-IMPEDANCE
12 AT26DF081A [Preliminary]
3600A–DFLASH–11/05

12 Page





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