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AD9267 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9267
Beschreibung 640 MSPS Dual Continuous Time Sigma-Delta Modulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD9267 Datasheet, Funktion
10 MHz Bandwidth, 640 MSPS
Dual Continuous Time Sigma-Delta Modulator
AD9267
FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: −88 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 416 mW
10 MHz real or 20 MHz complex bandwidth
1.8 V analog supply operation
On-chip PLL clock multiplier
On-chip voltage reference
Twos complement data format
640 MSPS, 4-bit LVDS data output
Serial control interface (SPI)
APPLICATIONS
Baseband quadrature receivers: CDMA2000, W-CDMA,
multicarrier GSM/EDGE, 802.16x, and LTE
Quadrature sampling instrumentation
GENERAL DESCRIPTION
The AD9267 is a dual continuous time (CT) sigma-delta (Σ-Δ)
modulator with −88 dBc of dynamic range over 10 MHz real
or 20 MHz complex bandwidth. The combination of high
dynamic range, wide bandwidth, and characteristics unique
to the continuous time Σ-Δ modulator architecture makes the
AD9267 an ideal solution for wireless communication systems.
The AD9267 has a resistive input impedance that significantly
relaxes the requirements of the driver amplifier. In addition, a
32× oversampled fifth-order continuous time loop filter attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input. The low noise figure of 15 dB relaxes the
linearity requirements of the front-end signal chain components,
and the high dynamic range reduces the need for an automatic
gain control (AGC) loop.
A differential input clock controls all internal conversion cycles.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. The digital output data is presented
as 4-bit, LVDS at 640 MSPS in twos complement format. A data
clock output (DCO) is provided to ensure proper latch timing
with receiving logic. Additional digital signal processing may be
required on the 4-bit modulator output to remove the out-of-band
noise and to reduce the sample rate.
VIN+A
VIN–A
VREF
CFILT
VIN–B
VIN+B
FUNCTIONAL BLOCK DIAGRAM
AVDD PDWNB PDWNA DRVDD
Σ -Δ
MODULATOR
AD9267
PHASE-
LOCKED
LOOP
Σ -Δ
MODULATOR
SERIAL
INTERFACE
OR±A
D3±A
D0±A
PLL_LOCKED
PLLMULT4
PLLMULT3
PLLMULT2
CLK+
CLK–
DCO±
D3±B
D0±B
OR±B
AGND
SDIO/
SCLK/
PLLMULT1 PLLMULT0
Figure 1.
CSB
DGND
The AD9267 operates on a 1.8 V power supply, consuming
416 mW. The AD9267 is available in a 64-lead LFCSP and
is specified over the industrial temperature range (−40°C
to +85°C).
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection, reducing or eliminating
the need for antialiasing filters.
4. Operates from a single 1.8 V power supply.
5. A standard serial port interface (SPI) supports various
product features and functions.
6. Features a low pin count, high speed LVDS interface with
data output clock.
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Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






AD9267 Datasheet, Funktion
AD9267
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.
Table 4.
Parameter1
CLOCK INPUT PARAMETERS
Input CLK Rate
CLK± Period
CLK± Duty Cycle
CLOCK INPUT PARAMETERS
Conversion Rate
CLK± Period
CLK± Duty Cycle
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
DCO± Propagation Delay (tDCO)
DCO± to Data Skew (tSKEW)
Aperture Uncertainty (Jitter, tJ)
WAKE-UP TIME
Power-Down Power
Standby Power
Sleep Power
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE3
SCLK Period (tSCLK)
SCLK Pulse Width High Time (tSHIGH)
SCLK Pulse Width Low Time (tSLOW)
SDIO to SCLK Set-Up Time (tSDS)
SDIO to SCLK Hold Time (tSDH)
CSB to SCLK Set-Up Time (tSS)
CSB to SCLK Hold Time (tSH)
Conditions/Comments
Using clock multiplier
Direct clocking
Temp Min
Full 30
Full 6.25
Full 40
Full 608
Full 1.48
Full 40
Full 160
Full -60
Full 180
Full
25°C
25°C
25°C
25°C
Full
Full 16
Full 16
Full 5
Full 2
Full 5
Full 2
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Output propagation delay is measured from CLK± 50% transition to data D0±x to D3±x 50% transition, with 5 pF load.
3 See Figure 42 and the Serial Port Interface (SPI) section.
Typ
50
640
1.5625
50
510
268
200
1
3
9
15
100
Timing Diagram
CLK±
DCO±
D0±x TO D3±x
tDCO
tPD
tSKEW
Figure 2. Timing Diagram
Max Unit
160 MSPS
33.3 ns
60 %
672 MSPS
1.72 ns
60 %
840 ps
570 ps
280 Ps
ps rms
Μs
μs
μs
ns
40 ns
ns
ns
ns
ns
ns
ns
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Rev. 0 | Page 6 of 24

6 Page









AD9267 pdf, datenblatt
AD9267
EQUIVALENT CIRCUITS
500
2V p-p DIFFERENTIAL
1.8V CM
500
Figure 20. Equivalent Analog Input Circuit
CVDD
CLK+
CLK–
CVDD
10k
90k
10k
30k
Figure 21. Equivalent Clock Input Circuit
DRVDD
SDIO
1k
Figure 22. Equivalent SDIO Input Circuit
SCLK
1k
30k
Figure 23. Equivalent SCLK Input Circuit
CSB
AVDD
26k1k
Figure 24. Equivalent CSB Input Circuit
DRVDD
VV
D– D+
VV
DGND
NOTES
1. D– AND D+ REFERS TO
THE D0±x TO D3±x PINS.
Figure 25. Equivalent Digital Output Circuit
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10µF
10k
0.5V
2.85k
3.5k
8.5k
TO CURRENT
GENERATOR
Figure 26. Equivalent VREF Circuit
Rev. 0 | Page 12 of 24

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