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PDF AD7191 Data sheet ( Hoja de datos )
| Número de pieza | AD7191 | |
| Descripción | Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7191 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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Pin-Programmable, Ultralow Noise, 24-Bit,
Sigma-Delta ADC for Bridge Sensors
AD7191
FEATURES
GENERAL DESCRIPTION
Pin-programmable output rate
Output data rate: 10 Hz, 50 Hz, 60 Hz, 120 Hz
Pin-programmable PGA
Gain: 1, 8, 64, 128
Pin-programmable power-down and reset
RMS noise: 15 nV @ 10 Hz (gain = 128)
Up to 21.5 noise free bits (gain = 1)
Internal or external clock
Bridge power-down switch
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
Simultaneous 50 Hz/60 Hz rejection
Internal temperature sensor
Power supply: 3 V to 5.25 V
Current: 4.35 mA
Temperature range: –40°C to +105°C
Package: 24-lead TSSOP
INTERFACE
2-wire serial
SPI, QSPI™, and MICROWIRE™ compatible
Schmitt trigger on SCLK
The AD7191 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) ADC. The on-chip low noise gain
stage means that signals of small amplitude can be interfaced
directly to the ADC. It contains two differential analog inputs.
The part also includes a temperature sensor that can be used for
temperature compensation.
For ease-of-use, all the features of the AD7191 are controlled by
dedicated pins. The on-chip PGA has a gain of 1, 8, 64, or 128,
supporting a full-scale differential input of ±5 V, ±625 mV,
±78 mV, or ±39 mV. The output data rate can be programmed
to 10 Hz, 50 Hz, 60 Hz, or 120 Hz. Simultaneous 50 Hz and 60 Hz
rejection is obtained when the output data rate is set to 10 Hz
or 50 Hz; 60 Hz only rejection is obtained when the output data
rate is set to 60 Hz. The AD7191 can be operated with the
internal clock, or an external clock can be used.
The part operates with a power supply of 3 V to 5.25 V. It
consumes a current of 4.35 mA. It is available in a 24-lead
TSSOP package.
APPLICATIONS
Weigh scales
Strain gauge transducers
www.DPatraeSshsueeret4mU.ecaosmurement
Medical and scientific instrumentation
AVDD
FUNCTIONAL BLOCK DIAGRAM
AGND DVDD DGND REFIN(+) REFIN(–)
AIN1
AIN2
AIN3
AIN4
AD7191
MUX
PGA
Σ-Δ
ADC
SERIAL
INTERFACE
AND CONTROL
LOGIC
DOUT/RDY
SCLK
PDOWN
CHAN
CLKSEL
BPDSW
TEMPERATURE
SENSOR
CLOCK
CIRCUITRY
PGA2
PGA1
MCLK1 MCLK2
Figure 1.
ODR2 ODR1 TEMP
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
Parameter1
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
POWER REQUIREMENTS3
Power Supply Voltage
AVDD − AGND
DVDD − DGND
Power Supply Currents
AIDD Current
DIDD Current
IDD (Power-Down Mode)
AD7191B
±10
10
Offset binary
3/5.25
2.7/5.25
0.85
3.6
5
0.4
0.6
1.5
3
Unit
μA max
pF typ
Test Conditions/Comments
V min/V max
V min/V max
mA max
mA max
mA max
mA max
mA max
mA typ
μA max
0.75 mA typical, gain = 1.
3 mA typical, gain = 8.
4 mA typical, gain = 64 or 128.
0.35 mA typical, DVDD = 3 V.
0.5 mA typical, DVDD = 5 V.
External crystal used.
1 Temperature range: −40°C to +105°C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Digital inputs equal to DVDD or DGND.
AD7191
www.DataSheet4U.com
Rev. A | Page 5 of 20
5 Page 
8,388,825
8,388,820
8,388,815
8,388,810
8,388,805
8,388,800
8,388,795
0
200 400 600 800 1000
SAMPLE
Figure 9. Noise (VREF = AVDD, Output Data Rate = 120 Hz,
Gain = 1)
150
100
50
0
www.DataSheet4U.com
CODE
Figure 10. Noise Distribution Histogram
(VREF = AVDD, Output Data Rate = 120 Hz, Gain = 1)
AD7191
5
4
3
2
1
0
–1
–2
–4 –3 –2 –1
0
1
2
3
4
VIN (V)
Figure 11. INL (Gain = 1)
20
15
10
5
0
–5
–10
–15
–20
–0.03
–0.02
–0.01
0
0.01 0.02 0.03
VIN (V)
Figure 12. INL (Gain = 128)
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7191.PDF ] | |
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