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LE25FW418A Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LE25FW418A
Beschreibung 4M-bit (512K X 8) Serial Flash Memory
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 27 Seiten
LE25FW418A Datasheet, Funktion
Ordering number : ENA1432
LE25FW418A
CMOS IC
4M-bit (512K×8) Serial Flash Memory
with High-Density Read Mode
Overview
The LE25FW418A is 512K×8bit Serial flash memory by 3.0V single power supply operation, and support serial
peripheral interface (S.P.I.). There are three kinds of erase functions, Small Sector (4K bytes) erase, Sector (64K bytes)
erase and Chip erase. Page program can program the arbitrary data from 1 byte to 256 byte. Program time is high speed,
1.5ms (Typ.). Moreover, The LE25FW418A makes the best use of the feature of the serial flash memory, and is stored in
8pin very small package. The LE25FW418A is best suited for applications that require re-programmable nonvolatile
storage of program memory.
LE25FW418A has also the High-Density read mode (hereafter, HD_READ mode) that is the most high-speed data
transfer in the world as the flash memory with serial interface. About eight times the data-transfer velocity can be achieved
without changing the clock frequency used in a usual serial flash memory by using this mode. For instance, it is possible to
read with 400Mbit/s in the maximum by using the HD_READ mode of 50MHz though a standard serial flash memory read
with 50Mbit/s or less.
Features
Read/write operations enabled by single 3.0V power supply: 2.7 to 3.6V supply voltage range
Operating frequency : 50MHz
Temperature range : 0 to +70°C,-40 to 85°C(Planning)
Continued on next page.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
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61709 SY 20090428-S00004 No.A1432-1/27






LE25FW418A Datasheet, Funktion
LE25FW418A
Outline of High-Density read mode (HD_READ mode) operation
LE25FW418A has the HD_READ mode in addition to two kinds of normal read (4 bus read and 5 bus read). The
HD_READ mode is greatly different from the normal mode in three points.
The first is the difference of the role of pins. Four pins (SO, WP, HOLD, SI) become I/O pins (SIO3 to SIO0) in the
HD_READ mode while the input pin (SI) and the output pin (SO) are only one in the normal mode respectively as
shown in Figure 2. Because SO, WP, HOLD and SI operate as I/O pin in the HD_READ mode, the setting of read
address and the outputting read data become to be done from four pins.
The second is the difference of the relation between the clock and the data output. The rising edge of SCK is made a
trigger for the address input and the falling edge of SCK is made a trigger for the data output in the normal mode.
However, both edges of rising and falling of SCK will be done to the address taking and the data outputting in the
HD_READ mode.
The third is the difference of the data composition at the time of reading. It is read by the ×16 bit in the HD_READ
mode though it is read by the ×8 bit in the normal read. Therefore, please fix least significant bit (LSB) : A0 to L in the
address input in HD_READ mode.
Pin Assignments
CS
SO
WP
VSS
1 8 VDD
2 7 HOLD
3 6 SCK
4 5 SI
Normal mode Top view
Entry
Slipping out
CS
SIO3
SIO2
VSS
1 8 VDD
2 7 SIO1
3 6 SCK
4 5 SIO0
HD_READ mode
Top view
Figure 5: Serial input / output timing diagram for HD_READ mode (CL=1.0)
tCSS
tCLHI tCLLO
tCLZ
CS
tAS tAH tAS tAH tAS tAH
tV2
tHO
SCK
SIO3
SIO2
SIO1
SIO0
“0”
A22
A21
A20
A3 data data
A2 data data
A1 data data
“0” data data
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No.A1432-6/27

6 Page









LE25FW418A pdf, datenblatt
LE25FW418A
4. Status Register
The Status Register's contents are shown in Table 4.
The Status Register can perform detection state of a device and setup of protection.
Table 4 Status Registers
Bit Name
Bit0 RDY
Bit1 WEN
Bit2 BP0
Bit3 BP1
Bit4 BP2
Bit5
Bit6
Bit7 SRWP
Logic
0
1
0
1
0
1
0
1
0
1
0
1
Function
Ready
Erase/Program
Write disabled
Write enabled
Block protect information
See status register descriptions on BP0, BP1, and BP2.
Reserved bits
Reserved bits
Status register write enabled
Status register write disabled
Power-on Time Information
0
0
Nonvolatile information
Nonvolatile information
Nonvolatile information
0
0
Nonvolatile information
4-1. Status Register Read
The contents of the status registers can be read using the status register read command. This command can be executed
even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 9 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first
to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized
to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by
returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is
continued. The data can be read by the status register read command at any time (even during a program or erase cycle).
Figure 9 Status Register Read
CS
SCK
SI
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 15 16 23
8CLK
05h
SO High Impedance
DATA DATA DATA
MSB MSB MSB
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