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PDF LTC4218 Data sheet ( Hoja de datos )
| Número de pieza | LTC4218 | |
| Descripción | Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC4218
Hot Swap Controller
FEATURES
■ Wide Operating Voltage Range: 2.9V to 26.5V
■ Adjustable, 5% Accurate (15mV) Current Limit
■ Current Monitor Output
■ Adjustable Current Limit Timer Before Fault
■ Powergood and Fault Outputs
■ Adjustable Inrush Current Control
■ 2% Accurate Undervoltage and Overvoltage
Protection
■ Available in 16-Lead SSOP and 16-Pin 5mm × 3mm
DFN Packages
APPLICATIONS
■ RAID Systems
■ ATCA, AMC, μTCA Systems
■ Server I/O Cards
■ Industrial
DESCRIPTION
The LTC®4218 is a Hot Swap™ controller that allows a board
to be safely inserted and removed from a live backplane.
An internal high side switch driver controls the gate of an
external N-channel MOSFET for supply voltages from 2.9V
to 26.5V. A dedicated 12V version (LTC4218-12) contains
preset 12V specific thresholds, while the standard LTC4218
allows adjustable thresholds.
The LTC4218 provides an accurate (5%) current limit with
current foldback limiting. The current limit threshold can
be adjusted dynamically using an external pin. Additional
features include a current monitor output that amplifies
the sense voltage for ground referenced current sensing.
Overvoltage, undervoltage and powergood monitoring
are also provided.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
12V, 6A Card Resident Application
2mΩ
Si7108DN
12V
10Ω
VOUT
12V
+ 6A
330μF
AUTO
RETRY
0.1μF
0.1μF
SENSE– GATE SOURCE
SENSE+
VDD
UV
LTC4218DHC-12
12V
10k
FLT PG
1k
0.01μF
TIMER
INTVCC
GND
IMON
20k
ADC
4218 TA01a
VIN
10V/DIV
IIN
1A/DIV
VOUT
10V/DIV
PG
10V/DIV
Power-Up Waveform
25ms/DIV
4218 TA01b
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LTC4218
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 12V unless otherwise noted.
IDD vs VDD
2.0
1.8
85°C
1.6
25°C
1.4
–40°C
1.2
1.0
0
5 10 15 20 25 30
VDD (V)
4218 G01
INTVCC Load Regulation
3.5
VDD = 5V
3.0
2.5 VDD = 3.3V
2.0
1.5
1.0
0.5
0
0 –2 –4 –6 –8 –10 –12 –14
ILOAD (mA)
4218 G02
UV Low-High Threshold
vs Temperature
1.234
1.232
1.230
1.228
1.226
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4218 G03
UV Hysteresis vs Temperature
0.10
0.08
0.06
Timer Pull-Up Current
vs Temperature
–110
–105
–100
–95
Current Limit Delay
1000
CGATE = 10nF
100
10
1
0.04
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4218 G04
Current Limit Threshold Foldback
16
14
12
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1.0 1.2
FB VOLTAGE (V)
4218 G07
–90
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4218 G05
Current Limit Adjustment
16
14
12
10
8
6
4
2
0
1k 10k 100k 1M
RSET (Ω)
10M
4218 G08
0.1
0
15 30 45 60 75
CURRENT LIMIT SENSE VOLTAGE
(VSENSE+ – VSENSE–) (mV)
4218 G06
ISET Resistor vs Temperature
22
21
20
19
18
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4218 G09
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LTC4218
APPLICATIONS INFORMATION
its threshold. The PG then pulls low to indicate output
power is no longer good.
If VDD drops below 2.65V for greater than 5μs or INTVCC
drops below 2.5V for greater than 1μs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
170mA current to the SOURCE pin.
Overcurrent Fault
The LTC4218 features an adjustable current limit with
foldback that protects the MOSFET when excessive load
current happens. To protect the switch during active cur-
rent limit, the available current is reduced as a function
of the output voltage sensed by the FB pin. A graph in the
Typical Performance Characteristics shows the current
limit versus FB voltage.
An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the time-out delay set by
the TIMER. Current limiting begins when the current sense
voltage between the SENSE+ and SENSE– pins reaches
3.75mV to 15mV (depending on the foldback). The GATE
pin is then brought down with a 170mA GATE-to-SOURCE
current. The voltage on the GATE is regulated in order to
limit the current sense voltage to less than 15mV. At this
point, a circuit breaker time delay starts by charging the
external timing capacitor from the TIMER pin with a 100μA
pull-up current. If the TIMER pin reaches its 1.2V thresh-
old, the external switch turns off (with a 250μA current
from GATE to ground). Next, the FLT pin is pulled low to
indicate an overcurrent fault has turned off the MOSFET.
For a given the circuit breaker time delay, the equation for
setting the timing capacitor’s value is as follows:
CT = TCB • 0.083[μF/ms]
After the switch is turned off, the TIMER pin begins dis-
charging the timing capacitor with a 2μA pull-down current.
When the TIMER pin reaches its 0.2V threshold, the switch
is allowed to turn on again if the overcurrent fault has been
cleared. Bringing the UV pin below 0.6V and then high will
clear the fault. If the TIMER pin is tied to INTVCC, then the
switch is allowed to turn on again (after an internal 100ms
delay) if the overcurrent fault is cleared.
Tying the FLT pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin has
ramped below 0.2V. In this auto retry mode, the LTC4218
repeatedly tries to turn on after an overcurrent at a period
determined by the capacitor on the TIMER pin.
The waveform in Figure 3 shows how the output latches
off following a short circuit. The drop across the sense
resistor is 3.75mV as the timer ramps up.
VOUT
10V/DIV
IOUT
2A/DIV
ΔVGATE
10V/DIV
TIMER
2V/DIV
1ms/DIV
4218 F03
Figure 3. Short-Circuit Waveform
Current Limit Adjustment
The default value of the active current limiting signal
threshold is 15mV. The current limit threshold can be
adjusted lower by placing a resistor on the ISET pin. As
shown in the Functional Diagram the voltage at the ISET
pin (via the clamp circuit) sets the CS amplifier’s built-in
offset voltage. This offset voltage directly determines the
active current limit value. With the ISET pin open, the volt-
age at the ISET pin is determined by the buffered reference
voltage. This voltage is set to 0.618V which corresponds
to a 15mV current limit threshold.
An external resistor placed between the ISET pin and ground
forms a resistive divider with the internal 20k sourcing
resistor. The divider acts to lower the voltage at the ISET
pin and therefore lower the current limit threshold. The
overall current limit threshold precision is reduced to ±11%
when using a 20k resistor to half the threshold.
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC4218.PDF ] | |
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