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PDF LMH6517 Data sheet ( Hoja de datos )
| Número de pieza | LMH6517 | |
| Descripción | IF and Baseband | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
November 10, 2008
LMH6517
Multi Standard, IF and Baseband, Dual, DVGA
General Description
The LMH6517 contains two high performance digitally con-
trolled variable gain amplifiers (DVGA). It has been designed
for use in narrowband and broadband IF sampling applica-
tions. Typically the LMH6517 drives a high performance ADC
in a broad range of mixed signal and digital communication
applications such as mobile radio and cellular base stations
where automatic gain control (AGC) is required to increase
system dynamic range.
Each channel of LMH6517 has an independent digitally con-
trolled attenuator and a high linearity, differential output am-
plifier. Each block has been optimized for low distortion and
maximum system design flexibility. Each channel can be in-
dividually disabled for power savings.
The LMH6517 digitally controlled attenuator provides precise
0.5 dB gain steps over a 31.5 dB range. On chip digital latches
are provided for local storage of the gain setting. Both serial
and parallel programming options are provided. A Pulse
mode is also offered where simple up or down commands can
change the gain one step at a time.
The output amplifier has a differential output allowing large
signal swings on a single 5V supply. The low impedance out-
put provides maximum flexibility when driving filters or analog
to digital converters.
The LMH6517 operates over the industrial temperature range
of −40°C to +85°C. The LMH6517 is available in a 32-Pin,
thermally enhanced, LLP package.
Features
■ Accurate, 0.5dB gain steps
■ 200Ω Resistive, differential input
■ Low impedance, differential output
■ Disable function for each channel
■ Parallel or serial gain control
■ SPI compatible serial bus
■ On chip register stores gain setting
■ Low sensitivity of linearity and phase to gain setting
■ Single 5V supply voltage
■ Small footprint LLP package
Key Specifications
■ Gain step size of 0.5 dB
■ Operating frequency Range of 1200 MHz
■ OIP3: 47 dBm @ 100 MHz
■ Noise figure 6 dB
■ Gain step accuracy: 0.15 dB
■ Supply current 80 mA per channel
Applications
■ Cellular base stations
■ IF sampling receivers
■ Instrumentation
■ Modems
■ Imaging
Typical Application
LMH™ is a trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation 300681
30068101
www.national.com
1 page  
wwPwi.nDatDaSehesect4Uri.cpomtions
Pin Number
Symbol
Description
Analog I/O
30, 11
29, 12
24, 17
IPA+, IPB+
IPA−, IPB−
OPA+, OPB+
Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not
exceed VCC or go below GND by more than 0.5V.
Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed
VCC or go below GND by more than 0.5V.
Amplifier non—inverting output. Internally biased to mid supply.
23, 18
OPA−, OPB−
Amplifier inverting output. Internally biased to mid supply.
Power
13, 15, 26, 28,
center pad
GND
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is the primary ground
connection.
14, 27
+5V
Power supply pins. Valid power supply range is 3V to 5.5V.
Common Control Pins
4, 5
MOD0, MOD1
Digital Mode control pins. These pins float to the logic hi state if left unconnected. See
below for Mode settings.
22, 19
ENA, ENB
Enable pins. Logic 1 = enabled state. See application section for operation in serial mode.
Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1)
25, 16
A0, B0
Gain bit zero = 0.5 dB step. Gain steps down from maximum gain (000000 = Maximum
Gain)
31, 10
A1, B1
Gain bit one = 1 dB step
32, 9
A2, B2
Gain bit two = 2 dB step
1, 8
A3, B3
Gain bit three = 4 dB step
2, 7
A4, B4
Gain bit four = 8 dB step
3, 6
A5, B5
Gain bit five = 16 dB step
21, 20
LATA, LATB
Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high.
Connect to ground if the latch function is not desired.
Digital Inputs Serial Mode
2 CLK Serial Clock
1 SDI Serial Data In (SPI Compatible) See application section for more details.
32 CS Serial Chip Select (SPI compatible)
31
SDO
Serial Data Out (SPI compatible)
3, 4, 6 — 10, 15, GND
16, 20, 21, 25, 26
Pins unused in Serial Mode, connect to DC ground.
Digital Inputs Pulse Mode
2, 7
UPA, UPB
Up pulse pin. A logic 1 pulse will increase gain one step.
1, 8
DNA, DNB
Down pulse pin. A logic 1 pulse will decrease gain one step.
1 & 2 or 7 & 8
Pulsing both pins together will reset the gain to maximum gain.
31, 32
S0A, S1A
Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1) = 1 dB; (1, 0) = 2 dB, and (1, 1) = 6
dB
10, 9
S0B, S1B
Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1) = 1 dB; (1,0) = 2 dB, and (1, 1) = 6
dB
3, 5, 6, 13, 15, 16, GND
25, 26
Pins unused in Pulse Mode, connect to DC ground.
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| PDF Descargar | [ Datasheet LMH6517.PDF ] | |
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