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PDF STA2065 Data sheet ( Hoja de datos )
| Número de pieza | STA2065 | |
| Descripción | infotainment application processor | |
| Fabricantes | STMicroelectronics | |
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STA2065
Cartesio™ family
infotainment application processor with embedded GPS
Data brief
Features
■ ARM1176 533/624 MHz host processor
– Cache: 32 KB instruction, 32 KB data
– Vector floating point unit
■ High performance embedded GPS subsystem
– Parallel acquisition engines for 8 GPS
satellites or 4 Galileo satellites
– 32 tracking channels for all satellites in view
– 5 correlators per channel for urban canyon
robustness
– Multibit signal processing hardware
■ Advanced power management
– Separated power islands for ultra low
power mode
– Dynamic core frequency scaling
– 512-Byte embedded SRAM for back-up
■ System infrastructure
– LP DDR/DDR2 controller: 16/32bit data
512 MB addressable. (333 MHz DDR2,
200 MHz LPDDR)
– Static memory controller (bootable):
NAND/NOR, SRAM
– One bank of 32 KB embedded SRAM
– 64-channel vector interrupt controller (VIC)
– 2 DMA controllers, 16 physical channels
– 32 DMA request for each controller
– Two external DMA requests are supported
■ Display and graphics
– Color LCD controller for STN,TFT or HR-
TFT panels with 24-bit parallel RGB
interface
– Integrated touch screen controller and ADC
– 3D advanced graphics acceleration
– Video input port (VIP) interface
– JPEG baseline profile decoder
■ High throuput interfaces
– 2 ports USB 2.0 OTG with integrated
physical layers
– 3 SD/MMC up to 8 bit data, 2 bootable
TFBGA372+100 (16x16x1.2mm)
■ Audio interfaces and features
– Four multichannel serial ports (I2S/TDM)
– SPDIF input interface
– C3 hardware reed-solomon decoder
– Sample rate converter
■ Standard interfaces
– Four 16-bit input capture/output compare
– Pulse width light modulator (PWL)
– Four autobaud UART
– Three I2C multimaster/slave interfaces
– Two synchronous serial port (SSP, SPI)
– Smartcard interface
– Five 32-bit GPIO ports
■ Two controller area network (CAN) in
automotive version
■ Programmable voltage IOs: 1.8 V, 2.5 V, 3.3 V
■ VIOON: 1.8 ±10%V, VDDON: VDD, 1.0 ±10%V
■ TFBGA 372+100 0.65 mm pitch package,
packing in tray
■ Ambient temperature range: -40 / +85 °C
Table 1. Device summary
Order code
Qualification
grade
CPU freq.
STA2065N Consumer 533 MHz
STA2065P Consumer 624 MHz
STA2065A Automotive 533 MHz
CAN
No
No
2x
July 2009
Doc ID16050 Rev 1
For further information contact your local STMicroelectronics sales office.
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2 System description
System description
2.1 MCU
ARM1176-JZF advanced risc machine CPU up to 624 MHz (with Vdd greater or equal to
1.20 V and under process and temperature worst case conditions).
2.2
2.2.1
Embedded memories
Embedded SRAM (eSRAM)
The embedded SRAM is 8K x 32 (32 KB).
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
System functions
System and reset controller (SRC)
This provides a control interface for clock generation components external to the subsystem.
It also controls system-wide and peripherals-specific energy management features.
PMU
The power manager module controls the SLEEP to DEEP-SLEEP modes transition,
controls the external voltage switches on the Vdd and Vddio, monitors the external power
supply (via two signals, Vddok and BATOK), can force the emergency entry of the SDRAM
in self-refresh, and controls the wake-up from DEEP-SLEEP mode.
DMA
Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from
these peripherals can be serviced immediately by the DMA Controller without CPU
interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported.
STA2065 features two DMA engines. Each DMA supports up to 8-channels and up to 32
requests.
Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts.
GPIOs
Four GPIO ports provide 160 programmable inputs or outputs that can be controlled in two
modes:
● software mode through an APB bus interface
● hardware mode through a hardware control interface
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System description
2.7.2
2.7.3
MHz. The same divisor will be from 2 to 16 when the PLL2 is running at 432 MHz, giving an
operating frequency in the range from 216 to 27 MHz.
The GPS baseband clock will be derived from the MCLK clock with a divider, internal to the
subsytem, by 1, 2,3 or 4, under ARM11 control. RFCLK is the clock received from the RF
front-end chip.
Touchscreen controller/ADC
STA2065 embeds a 4-wire Touch Screen Controller. The Touch Screen Controller main
characteristics are:
● Active Window Clip
● Movements Tracking
● 12-bit SAR ADC resolution when used for Touch screen (with averaging)
● Measurement oversampling from 2 to 8
● Up to 128 coordinates FIFO, with programmable FIFO threshold
● ADC minimum conversion time of 1 μs
● Capability to support 4 additional analog inputs for auxiliary functions like battery
voltage monitoring and accessory control.
The ADC of the Touch Screen Controller can be also used for the conversion of external
analog signals. In this case the ADC has a 10-bit resolution (its native resolution).
Multisupply IO ring
STA2065 has multivoltage IOs capable of supporting 1.8V, 2.5V or 3.3V interfaces. The
rings are defined as follows:
● A: All peripherals with exception of what belongs to other rings
● B: LCD
● C: DRAM
● D: FSMC
● E: MMC1 (GPIO40-47, GPIO76-82), CAN0
The default voltage applied to each ring will be at reset time will be:
● A: 1.8V
● B: 1.8V
● C: 1.8V
● D: 1.8V
● E: 3.3V
The “Always ON” ring remains separated as in the current STA2065 and supplied by VIOON.
Doc ID16050 Rev 1
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