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PDF PO74HSTL314A Data sheet ( Hoja de datos )
| Número de pieza | PO74HSTL314A | |
| Descripción | 3.3V 2:4 Differential Clock/Data Fanout Buffer | |
| Fabricantes | Potato Semiconductor Corporation | |
| Logotipo |  |
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PO74HSTL314A
3.3V 2:4 Differential Clock/Data Fanout Buffer
500MHz HSTL Potato Chip
07/28/06
FEATURES:
. Patented Technology
. Four HSTL differential outputs
. The two pair of LVDS/LVPECL/HSTL/ differential
or single-ended inputs
. Hot-swappable/-insertable
. Operating frequency up to 500MHz with 2pf load
. Operating frequency up to 480MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. Very low output pin to pin skew < 80ps
. Very low pulse skew < 80ps
. 2.8-ns propagation delay (typical)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin 209 mil SSOP package
DESCRIPTION:
The PO74HSTL314 is a low-skew, 2-to-4 differential
fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications.
The device is implemented on 0.35um CMOS technology
and has a fully differential internal architecture that is
optimized to achieve low signal skews at operating
frequencies of up to 500MHz .
The device features two differential input paths that are
multiplexed plexed internally. This mux is controlled by
the CLK_SEL pin. The PO74HSTL314 may function not
only as a differential clock buffer but also as a signal-level
translator and fanout on HSTL or LVCMOS / LVTTL
single-ended signal to four HSTL differential loads.
Since the PO74HSTL314 introduces negligible jitter to the
timing budget, it is the ideal choice for distributing high
frequency, high precision clocks across back-planes and
boards in communication systems.
Pin Configuration
VCC
NC
VCC
CLK_SEL
CLKA
CLKA#
CLKB
CLKB#
VEE
VCC
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q0
18 Q0#
17 Q1
16 Q1#
15 Q2
14 Q2#
13 Q3
12 Q3#
11 VCC
Logic Block Diagram
VCC
CLKA
CLKA#
VEE
VCC
CLKB
CLKB#
CLK_SEL
VEE
VEE
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
1
Copyright © Potato Semiconductor Corporation
1 page  
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PO74HSTL314A
3.3V 2:4 Differential Clock/Data Fanout Buffer
500MHz HSTL Potato Chip
07/10/06
Test Waveforms
FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS
VCC= 3.3V
VIH
VPP RANGE
VPP 0V-VCC
VIL
VEE=0.0V
VCC
VEE
FIGURE 2. HSTL/HSTL OUTPUT
tr,tf,
20-80%
VO
FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew
for both CLKA or CLKB to output pair
INPUT
CLOCK
OUTPUT
CLOCK
TPLH
TPD
ANOTHER
OUTPUT
CLOCK
TPHL
VPP
tSK(O)
VO
5
Copyright © Potato Semiconductor Corporation
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