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ADV3203 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV3203
Beschreibung (ADV3202 / ADV3203) 32 X 16 Buffered Analog Crosspoint Switch
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADV3203 Datasheet, Funktion
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FEATURES
Large, 32 × 16, nonblocking switch array
G = +1 (ADV3202) or G = +2 (ADV3203) operation
32 × 32 pin-compatible version available (ADV3200/ADV3201)
Single +5 V, dual ±2.5 V, or dual ±3.3 V supply (G = +2)
Serial programming of switch array
2:1 OSD insertion mux per output
Input sync-tip clamp
High impedance output disable allows connection of
multiple devices with minimal output bus load
Excellent video performance
60 MHz 0.1 dB gain flatness
0.1% differential gain error (RL = 150 Ω)
0.1° differential phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: >300 MHz
Slew rate: >400 V/μs
Low power: 1 W
Low all hostile crosstalk: −48 dB @ 5 MHz
Reset pin allows disabling of all outputs
Connected through a capacitor to ground, provides
power-on reset capability
176-lead exposed pad LQFP package (24 mm × 24 mm)
APPLICATIONS
CCTV surveillance
Routing of high speed signals, including
Composite video (NTSC, PAL, S, SECAM)
RGB and component video routing
Compressed video (MPEG, wavelet)
Video conferencing
GENERAL DESCRIPTION
The ADV3202/ADV3203 are 32 × 16 analog crosspoint switch
matrices. They feature a selectable sync-tip clamp input for
ac-coupled applications and a 2:1 on-screen display (OSD)
insertion mux. With −48 dB of crosstalk and −80 dB isolation
at 5 MHz, the ADV3202/ADV3203 are useful in many high
density routing applications. The 0.1 dB flatness out to 60 MHz
makes the ADV3202/ADV3203 ideal for both composite and
component video switching.
The 16 independent output buffers of the ADV3202/ADV3203
can be placed into a high impedance state for paralleling cross-
point outputs so that off-channels present minimal loading to
300 MHz, 32 × 16 Buffered
Analog Crosspoint Switch
ADV3202/ADV3203
FUNCTIONAL BLOCK DIAGRAM
VPOS VNEG DVCC DGND
CLK
DATA IN
193-BIT SHIFT REGISTER
UPDATE
CS
RESET
ENABLE/
BYPASS
97 96
PARALLEL LATCH
96
16 × 5:32
DECODERS
ADV3202
(ADV3203)
16 ENABLE/
DISABLE
SYNC-TIP
CLAMP
512
OUTPUT
BUFFER
G = +1
(G = +2)
DATA
OUT
32
INPUTS
...
...
SWITCH OSD
... ...MATRIX MUX
16
OUTPUTS
16
REFERENCE
16
VCLAMP
OSD
OSD VREF
INPUTS SWITCHES
Figure 1.
an output bus if building a larger array. The ADV3202 has a
gain of +1 while the ADV3203 has a gain of +2 for ease of use in
back-terminated load applications. A single +5 V supply, dual
±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used
while consuming only 195 mA of idle current with all outputs
enabled. The channel switching is performed via a double
buffered, serial digital control that can accommodate daisy
chaining of several devices.
The ADV3202/ADV3203 are packaged in a 176-lead exposed
pad LQFP package (24 mm× 24 mm) and are available over the
extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






ADV3203 Datasheet, Funktion
wwAwD.DVat3aS2h0ee2t4/UA.cDomV3203
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Supply Voltage (VPOS − VNEG)
Digital Supply Voltage
(DVCC − DGND)
Ground Potential Difference
(VNEG − DGND)
Maximum Potential Difference
DVCC − VNEG
Disabled Outputs
ADV3202 (|VOSD − VOUT|)
ADV3203 (|VOSD −(VOUT+VREF)/2|)
|VCLAMP − VINxx|
VREF Input Voltage
ADV3202
ADV3203
Analog Input Voltage
Digital Input Voltage
Output Voltage
(Disabled Analog Output)
Output Short-Circuit Duration
Output Short-Circuit Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering, 10 sec)
Junction Temperature
Rating
7.5 V
6V
+0.5 V to –4 V
9.4 V
<3 V
<3 V
6V
VPOS – 3.5 V to VNEG + 3.5 V
VPOS – 4 V to VNEG + 4 V
VNEG to VPOS
DVCC
(VPOS − 1 V) to (VNEG + 1 V)
Momentary
45 mA
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
176-Lead LQFP_EP
θJA Unit
16 °C/W
POWER DISSIPATION
The ADV3202/ADV3203 are operated with ±2.5 V, +5 V, or
±3.3 V supplies and can drive loads down to 150 Ω, resulting in
a large range of possible power dissipations. For this reason,
extra care must be taken while derating the operating conditions
based on ambient temperature.
Packaged in a 176-lead exposed-pad LQFP, the ADV3202/
ADV3203 junction-to-ambient thermal impedance (θJA) is
16°C/W. For long-term reliability, the maximum allowed
junction temperature of the die should not exceed 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in stresses exerted on the die by
the package. Exceeding a junction temperature of 175°C for an
extended period can result in device failure. Figure 3 shows the
range of allowed internal die power dissipations that meet these
conditions over the −40°C to +85°C ambient temperature range.
When using Figure 3, do not include external load power in the
maximum power calculation, but do include load current
dropped on the die output transistors.
9
TJ = 150°C
8
7
6
5
4
3
15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Die Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 6 of 20

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ADV3203 pdf, datenblatt
wwAwD.DVat3aS2h0ee2t4/UA.cDomV3203
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.7
–0.5
–0.3 –0.1
0.1
0.3
INPUT DC OFFSET (V)
0.5
0.7
Figure 11. ADV3202 Differential Phase, Carrier Frequency = 3.58 MHz,
Subcarrier Amplitude = 300 mV p-p
8
6
4
INxx
2
OSDxx
0
–2
–4
–6
1 10 100 1k
FREQUENCY (MHz)
Figure 12. ADV3203 Small Signal Frequency Response, 200 mV p-p
8
6
OSDxx
INxx
4
2
0
–2
–4
–6
1 10 100 1k
FREQUENCY (MHz)
Figure 13. ADV3203 Large Signal Frequency Response, 2 V p-p
0.12
0.08
0.04
0
–0.04
–0.08
OSDxx
INxx
–0.12
0 2 4 6 8 10 12 14 16 18 20
TIME (ns)
Figure 14. ADV3203 Small Signal Pulse Response, 200 mV p-p
1.2
0.8
0.4
0
–0.4
OSDxx
–0.8 INxx
–1.2
0 2 4 6 8 10 12 14 16 18 20
TIME (ns)
Figure 15. ADV3203 Large Signal Pulse Response, 2 V p-p
600
400
RISING EDGE
200
0
–200
–400
FALLING EDGE
–600
0 2 4 6 8 10 12 14 16 18 20
TIME (ns)
Figure 16. ADV3203 Slew Rate
Rev. 0 | Page 12 of 20

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