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ISL12058 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ISL12058
Beschreibung Low Cost and Low Power I2C-Bus Real Time Clock/Calendar
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 19 Seiten
ISL12058 Datasheet, Funktion
www.DataSheet4U.com
ISL12058
®
Low Cost and Low Power I2C-Bus™ Real Time Clock/Calendar
Data Sheet
June 15, 2009
FN6756.0
Low Power and Low Cost RTC with Alarm
Function
The ISL12058 device is a low power real time clock with
clock/calendar, and alarm function.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Pinouts
ISL12058
(8 LD SOIC, MSOP)
TOP VIEW
X1 1
X2 2
NC 3
GND 4
8 VDD
7 IRQ/FOUT
6 SCL
5 SDA
ISL12058
(8 LD 2x2 µTDFN, 8 LD 3x3 TDFN)
TOP VIEW
X1 1
X2 2
NC 3
GND 4
8 VDD
7 IRQ/FOUT
6 SCL
5 SDA
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Date, Month, and Year
• 4 Selectable Frequency Outputs
• 2 Alarms
- Settable to the Second, Minute, Hour, Day of the Week,
Date, or Month
• I2C Interface
- 400kHz Data Transfer Rate
• Small Package Options
- 8 Ld 2mmx2mm µTDFN Package
- 8 Ld 3mmx3mm TDFN Package
- 8 Ld MSOP Package
- 8 Ld SOIC Package
- Pb-Free (RoHS Compliant)
• Low Cost 3V Alternative to ISL1208 and ISL12082
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• Point Of Sale Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
I2C-busAll other trademarks mentioned are the property of their respective owners.






ISL12058 Datasheet, Funktion
ISL12058
www.SDaDtaAShevest4US.cComL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Symbol Table
WAVEFORM
INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A Center Line is
High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 3.0V
5.0V
SDA,
IRQ/FOUT
1533Ω
FOR VOL= 0.4V
AND IOL = 3mA
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH VDD = 3.0V, VPULLUP = 5.0V
6 FN6756.0
June 15, 2009

6 Page









ISL12058 pdf, datenblatt
ISL12058
www.DataSheet4U.com
ALARM1
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
A1SC 0 0 0 0 0 0 0 0 00h Seconds disabled
A1MN 1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
A1HR 1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
A1DT
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
A1MO 1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
A1DW 0 0 0 0 0 0 0 0 00h Day of week
disabled
B. Also the ALME bit must be set as follows:
CONTROL
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
INT 0 1 x x x 1 0 1 45h Enable Alarm1,
and Alarm1
Interrupt to
IRQ/FOUT
xx indicate other control bits and these bit can be set to 0 or
1.
After these registers are set, the Alarm1 interrupt will be
generated when the RTC advances to exactly 11:30am on
January 1 (after seconds changes from 59 to 00) by setting
the A1F bit in the status register to “1” and also bringing the
IRQ/FOUT output low.
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
make the comparison. Note that there are no alarm bytes for
second, month and year. When all the enable bits are set to
“0” with ALM2E set to “1”, the Alarm2 will triggered once a
minute when second hits “00”.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit can be set to “0” with a
write or use the ARST bit auto reset function.
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
SELECTION
A2DW/DT A2M2 A2M3 A2M4
ALARM2 Interrupt
0 0 0 0 Every Minute (Second=00)
0 100
Match Minute
0 010
Match Hour
0 001
Match Date
1 001
Match Day
0 1 1 0 Match Minute and Hour
0 1 0 1 Match Minute and Date
0
011
Match Hour and Date
0 1 1 1 Match Minute, Hour, and Date
1 1 1 0 Match Minute and Hour
1 1 0 1 Match Minute and Day
1 0 1 1 Match Hour and Day
1 1 1 1 Match Minute, Hour, and Day
Following is example of Alarm2 Interrupt.
Example – A single alarm will occur on every Monday at
20:00 military time (Monday is when DW = 1).
A. Set Alarm registers as follows:
ALARM2
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A2MN 0 0 0 0 0 0 0 0 00h Minutes disabled
A2HR 1 1 1 0 0 0 0 0 E0h Hours set to 20,
enabled
A2DW/DT 1 1 0 0 0 0 0 1 C1h Day set to Monday,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
I2C Serial Interface
The ISL12058 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12058 operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
12 FN6756.0
June 15, 2009

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