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PDF KK4071B Data sheet ( Hoja de datos )
| Número de pieza | KK4071B | |
| Descripción | Quad 2-Input OR Gate High-Voltage Silicon-Gate CMOS | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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Quad 2-Input OR Gate
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4071B
The KK4071B OR gates provide the system designer wich direct
emplementation of the positive-logic OR function.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4071BN Plastic
KK4071BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
L
H
H
H
1
1 page  
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N SUFFIX PLASTIC DIP
(MS - 001AA)
A
14
1
8
B
7
FL
C
-T- SEATING
PLANE
N
G
KM
D
J
H
NOTES:
0.25 (0.010) M T
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
KK4071B
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimension, mm
MIN MAX
18.67 19.69
6.1 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.2 0.36
0.38
D SUFFIX SOIC
(MS - 012AB)
14
H
A
8
BP
1G
7
C
R x 45
-T-
D
NOTES:
SEATING
K PLANE
0.25 (0.010) M T C M
J
F
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
H
MJ
K
M
P
R
Dimension, mm
MIN MAX
8.55 8.75
3.8 4
1.35 1.75
0.33 0.51
0.4 1.27
1.27
5.27
0° 8°
0.1 0.25
0.19 0.25
5.8 6.2
0.25 0.5
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet KK4071B.PDF ] | |
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