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PDF KK4042B Data sheet ( Hoja de datos )
| Número de pieza | KK4042B | |
| Descripción | High-Voltage Silicon-Gate CMOS | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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Quad Clocked «D» Latch
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4042B
KK4042B types contain four latch circuits, each strobed by a common
clock. Complementary buffered outputs are available from each circuit.
The impedance of the n- and p-channel output devices is balanced and all
outputs are electrically identical. Information present at the data input is
transferred to outputs Q and Q during the CLOCK level which is
programmed by the POLARITY input. For POLARITY = 0 the transfer
occurs during the 0 CLOCK level and for POLARITY = 1 the transfer
occurs during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are present.
When a CLOCK transition occurs (positive for POLARITY = 0 and
negative for POLARTY = 1) the information present at the input during
the CLOCK transition is retained at the outputs until an opposite CLOCK
transition occurs.
The KK4042B types are supplied in 16-lead hermetic dual-in-line
ceramic packages (D and F suffixes); 16-lead dual-in-line plastic package
(E suffix), and in chip form (H suffix).
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4042BN Plastic
KK4042BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Clock
Polarity
00
10
11
01
Outputs
Q
D
Latch
D
Latch
1
1 page  
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KK4042B
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet KK4042B.PDF ] | |
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