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PDF PI2EQX5804C Data sheet ( Hoja de datos )
| Número de pieza | PI2EQX5804C | |
| Descripción | 5.0Gbps 4-Lane PCIe 2.0 ReDriver W/ Equalization & Emphasis | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™
with Equalization & Emphasis
Features
• Up to 5.0Gbps PCIe® 2.0 Serial ReDriver™
• Supporting 8 differential channels or 4 lanes of PCIe Interface
• Pin strapped and I2C configuration controls
• Adjustable receiver equalization
• Adjustable transmitter amplitude and de-emphasis
• Variable input an output termination
• 1:2 channel broadcast
• Channel loop-back
• Electrical Idle fully supported
• Receiver detect and individual output control
• Single supply voltage, 1.2V ± 0.05V
• Power down modes
• Packaging: 100-contact LBGA, Pb-free & Green
Description
Pericom Semiconductor’s PI2EQX5804C is a low power, PCIe®
compliant signal ReDriver™. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums
by reducing Inter-symbol interference.
PI2EQX5804C supports eight 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCIe signal before the ReDriver, whereas
the integrated de-emphasis circuitry provides flexibility with
signal integrity of the signal after the ReDriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5804C also provides power management Stand-by mode
operated by a Power Down pin.
Block Diagram
xyRx+
xyRx-
xyTx+
xyTx-
+
−
+
− Equalizer
Input level detect
to control logic
Output
Controls
+
−
xyTx+
xyTx-
+
−
Output
Controls
A
B
Input level detect
to control logic
Equalizer
+
−
+
−
Data Lane Repeats 4 Times
xyRx+
xyRx-
SELy_x
Sy_x
Dy_x
DE_x
PD#
SDA
SCL
Control registers
& logic
Power
Management
I2C Control
Mode
LB#
RXD_x
RES_x
Ax
Pin Configuration (Top-Side View)
12
34
56 7 8
9 10
A VDD B0TX- B0TX+ VDD SCL SDA VDD B0RX+ B0RX- VDD
B A1RX+ GND GND A0RX - DE_A VDD A0TX- GND GND A1TX+
C A1RX- GND GND A0RX+ NC PD# A0TX+ GND GND A1TX-
D VDD B1TX+ B1TX- VDD D2_A NC VDD B1RX- B1RX+ VDD
E SEL0_A SEL1_A SEL2_A D0_A D1_A S0_A RXD_A S1_A SIG_A RX50_A
F RX50_B SIG_B S1_B RXD_B S0_B A1 SEL2_B LB# SEL1_B SEL0_B
G VDD A2RX- A2RX+ VDD MODE D0_B VDD A2TX+ A2TX - VDD
H B2TX+ GND GND B3TX- DE_B A0 B3RX- GND GND B2RX+
J B2TX- GND GND B3TX+ RESET# D1_B B3RX+ GND GND B2RX-
K VDD A3RX+ A3RX- VDD D2_B A4
VDD A3TX- A3TX+ VDD
09-0001
1
PS8926B
06/08/09
1 page  
www.DataSheet4U.com
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Equalizer Configuration
The PI2EQX5804C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) re-
sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-
frequency signal components. Because either too little, or too much, signal compensation may be non-optimal
eight levels are provided to adjust for any application.
Equalizer configuration is performed in two ways determined by the state of the MODE pin. When the device
first powers up, the SELx_[A:B] input pins are read into the appropriate control registers to set the equalization
characteristic. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
Each group of four channels, A and B, has separate equalization control, and all four channels within the group
are assigned the same configuration state. The Equalizer Selection table below describes pin strapping options
and associated operation of the equalizer. Refer to the section on I2C programming for information on soft-
ware configuration of the equalizer.
Equalizer Selection
SEL2_[A:B]
0
0
0
0
1
1
1
1
SEL1_[A:B]
0
0
1
1
0
0
1
1
SEL0_[A:B]
0
1
0
1
0
1
0
1
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
Output Configuration
The PI2EQX5804C provides flexible output strength and emphasis controls to provide the optimum signal to
pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye open-
ing. Control of output configuration is grouped for the A and B channels, so that each channel within the
group has the same setting.
Output configuration is performed in two ways depending on the state of the MODE pin. When the device
first powers up, the Sx_[A:B], and Dx_[A:B] input pins are read into the appropriate control registers to set the
power-on state. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
The Output Swing Control table shows available configuration settings for output level control, as specified
using the Sx_y pins and registers.
09-0001
5
PS8926B
06/08/09
5 Page 
www.DataSheet4U.com
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit (MSB) first (see the I2C Data Transfer diagram). The
PI2EQX5804C will never hold the clock line SCL LOW to force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of con-
figuration bytes. An offset byte presented by a host to the PI2EQX5804C is not used.
Addressing
Up to eight PI2EQX5804C devices can be connected to a single I2C bus. The PI2EQX5804C supports 7-bit
addressing, with the LSB indicating either a read or write operation. The address for a specific device is deter-
mined by the A0, A1 and A4 input pins.
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 Program 0 0
Programmable
1=R, 0=W
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH)
during the acknowledge clock pulse, the PI2EQX5804C will pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I2C
Data Transfer diagram. The PI2EQX5804C will generate an acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5804C
will watch the next byte of information for a match with its address setting. When a match is found it will
respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge
bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the first data byte fol-
lowing the address byte is a dummy or fill byte that is not used by the PI2EQX5804C. This byte is provided
to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
09-0001
11
PS8926B
06/08/09
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet PI2EQX5804C.PDF ] | |
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