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PI2EQX3201 Schematic ( PDF Datasheet ) - Pericom Semiconductor Corporation

Teilenummer PI2EQX3201
Beschreibung 3.2Gbps 2 Differential Channel Serial Re-driver
Hersteller Pericom Semiconductor Corporation
Logo Pericom Semiconductor Corporation Logo 




Gesamt 7 Seiten
PI2EQX3201 Datasheet, Funktion
www.DataSheet4U.com
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
Features
• Two 3.2Gbps differential signal
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• One Spread Spectrum Reference Clock Buffer Output
• 100Ω Differential CML I/O’s
• Low Power (100mW per Channel)
• Stand-by Mode – Power Down State
• VCC Operating Range: 1.8V ±0.1V
• Built in Clock Buffer
• Packaging (Pb-free & Green):
— 36-pad TQFN (ZF36)
Description
Pericom Semiconductor’s PI2EQX3201 is a low power, signal
re-driver. The device provides programmable equalization,
amplification, and de-emphasis by using 4 select bits, SEL[0:3],
to optimize performance over a variety of physical mediums by
reducing Inter-symbol interference. PI2EQX3201 supports two
100 Differential CML data I/O’s between the Protocol ASIC to
a switch fabric, across a backplane, or extends the signals across
other distant data pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the signal before the re-driver. Whereas the
integrated de-emphasis circuitry provides flexibility with signal
integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3201 also provides power management Stand-by mode
operated by a Bus Enable pin.
Block Diagram
Pin Description
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36 35 34 33 32 31 30 29
VDD 1
28 VDD
AI+ 2
27 A0+
AI-
GND
3
4
26 A0-
25 GND
AVDD
VDD
B0+
5
6
7
GND
24 AGND
23 VDD
22 BI+
B0- 8
21 BI-
GND 9
20 GND
VDD 10
19 IREF
11 12 13 14 15 16 17 18
06-0086
1
PS8818
02/28/06






PI2EQX3201 Datasheet, Funktion
www.DataSheet4U.com
PI2EQX3201
3.2Gbps 2 Differential Channel Serial Re-driver
with built-in Equalization and De-emphasis
AC Switching Characteristics for Clock Buffer (VDD = 1.8 ±0.1V, AVDD = 1.8 ±0.1V) (3)
Symbol
Parameters
Min
Trise / Tfall Rise and Fall Time (measured between 0.175V to 0.525V) (1)
125
ΔTrise /
ΔTfall
Rise and Fall Time Variation
VHIGH
Voltage High including overshoot
660
VLOW
Voltage Low including undershoot
-200
VCROSS
Absolute crossing point voltages
200
ΔVCROSS
TDC
Total Variation of Vcross over all edges
Duty Cycle (input duty cycle = 50%) (2)
45
Max.
525
75
900
550
250
55
Notes:
1. Measurement taken from Single Ended waveform.
2. Measurement taken from Differential waveform.
3. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF.
Units
ps
mV
%
Notes
1
1
1
1
1
1
2
Configuration Test Load Board Termination
CLKBUF
475
1%
Rs
33
5%
Rs
33
5%
Rp
49.9
1%
TLA
Rp
49.9
1%
TLB
2pF
5%
Clock
Clock#
2pF
5%
Figure 2. Configuration test load board termination
Note:
• TLA and TLB are 3” transmission lines.
06-0086
6
PS8818
02/28/06

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